Processor 6 or 8 core, 1.0 GHz UltraSPARC T1 processor
Architecture SPARC V9 architecture, ECC Protected
Cache per processor 16 KB instruction, 8 KB primary data cache, 3 MB integrated L2
Date: Sat, 4 Nov 2006 10:02:48 -0800
From: Tom Moran <[log in to unmask]>
Are there 8 separate caches or do they share? How big is cache?
Karl A. Nyberg wrote:
>I hope soon to be the recipient of an evaluation Sun Niagara T1000 via their
>"Try and Buy" program (https://www.sun.com/tryandbuy/index.jsp) and would
>like to try to make it available for folks with an application that they
>would like to run in this kind of an environment. It will be an 8-core
>machine (which, with their "4 threads per core pipelining", well, you get
>the idea...). If you are interested, please drop me a line.
>Applications with low floating point requirements only need apply... Only
>one FPU on the chip...
>-- Karl --
-- Karl --