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Subject:
From:
Nathan Binkert <[log in to unmask]>
Reply To:
Nathan Binkert <[log in to unmask]>
Date:
Sun, 9 Nov 2008 14:06:05 -0800
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This is the 1st November 2008 Digest of SIGARCH Messages (sigarch-nov08a):

* SC08 BOF on the Cell Processor
Submitted by Ashok Srinivasan <[log in to unmask]>

* CFP: 23rd International Conference on Supercomputing
http://www.ics-conference.org
Submitted by Michael Gschwind <[log in to unmask]>

* ISCA 2009: Call for Workshops and Tutorials
Submitted by Simha Sethumadhavan <[log in to unmask]>

* CFP: PACT 2009
http://pact09.renci.org
Submitted by Mohamed Zahran <[log in to unmask]>

* Deadline Extension for the SMART'09
http://www.hipeac.net/smart-workshop.html
Submitted by Grigori Fursin <[log in to unmask]>

* CFP: HPCA Workshop on 3D Integration and Interconnect-centric Architectures
Submitted by Eren Kursun <[log in to unmask]>

- Nathan Binkert
Researcher, HP Labs
SIGARCH Information Director <[log in to unmask]>

* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
 mail [log in to unmask] with message body: unsubscribe SIGARCH-MEMBERS

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* SC08 BOF on the Cell Processor
Submitted by Ashok Srinivasan <[log in to unmask]>

  We are organizing a Birds-of-a-Feather session on the Cell processor
  at SC08, Wed Nov 19, 12:15 pm - 1:15 pm. We seek input from the Cell
  user community on questions they would like addressed during the
  BOF. Please email us at [log in to unmask] or [log in to unmask]
  or [log in to unmask], if you have some questions you would like
  discussed. The current list of questions is available at:
  http://sti.cc.gatech.edu (please select the "SC08 BOF" tab on the
  left).

Organizers: David Bader, Georgia Tech.; Michael Perrone, IBM Research;
Ashok Srinivasan, Florida State University

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* CFP: 23rd International Conference on Supercomputing
http://www.ics-conference.org
Submitted by Michael Gschwind <[log in to unmask]>

                         CALL FOR PAPERS

         23rd International Conference on Supercomputing

                 http://www.ics-conference.org

                        June 9-11, 2009

                 IBM T.J. Watson Research Center
                  Metro New York City Area, USA

                    Sponsored by ACM/SIGARCH


ICS is the premier international forum for the presentation of
research results in high-performance computing systems.  Next year the
conference will be held at the IBM T.J. Watson Research Center in
Yorktown Heights, NY.  The Center is located in a scenic area of State
of New York and is within easy reach of New York City.

Papers are solicited on all aspects of research, development, and
application of high-performance experimental and commercial systems,
including:

* Computationally challenging scientific and commercial applications;
  Application studies and experiences: porting and tuning for
  performance and scalability

* Architecture and hardware aspects: high-performance and power-aware
  microarchitectures, multithreading, multicore and multiprocessor
  systems optimization to exploit different levels of parallelism,
  interconnection networks, memory organization and parallel storage
  and I/O

* High-performance computational and programming models; new languages
  and middleware for high performance computing; autotuners and
  function-specific code generators

* Hardware and software aspects of computational accelerators for
  supercomputing, such as Cell, GPGPUs, and FPGAs

* Software aspects: programming models, restructuring and optimizing
  compilers and runtime systems, kernel and application development
  and performance tuning tools, operating systems

* Novel infrastructures for Internet, Grid and Cloud computing;
  Autonomic components at all levels

* Performance evaluation studies and theoretical underpinnings of any
  of the above topics

* Large scale installations in the Petaflop era: design, scaling, power,
  and reliability, including case studies and experience reports


Papers should not exceed 6,000 words, and should be submitted
electronically, in PDF format using the ICS'09 submission web
site. Submissions should be blind.  The review process will include a
rebuttal period. Please refer to the ICS09 web site for detailed
instructions.

Workshop and tutorial proposals are also be solicited and due by
January 15, 2009.  For further information and future updates, refer
to the ICS'09 web site at http://www.ics-conference.org or contact the
General or Program Chairs.

Important Dates
Abstract  submission:  January 12, 2009
Paper submission:      January 19, 2009
Author notification:   March 23, 2009
Final papers:          April 24, 2009


GENERAL CO-CHAIRS
Michael Gschwind, IBM TJ Watson
Alex Nicolau, UC Irvine

PROGRAM CO-CHAIRS
Valentina Salapura, IBM TJ Watson
Jos=E9 Moreira, IBM TJ Watson

FINANCE CHAIR
Dimitris Nikolopoulos, Virginia Tech

PUBLICATIONS CHAIR
Pin Zhou, IBM Almaden

PUBLICITY CO-CHAIRS
Franz Franchetti, CMU

WORKSHOPS & TUTORIALS CO-CHAIRS
Gabriel Silberman, CA Labs
Mohamed Zahran, CUNY

WEB & SUBMISSIONS CO-CHAIRS
Eduard Ayguade, BSC & UPC
Alex Ramirez, BSC & UPC


For more information, please visit the conference web site at
http://www.ics-conference.org

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* ISCA 2009: Call for Workshops and Tutorials
Submitted by Simha Sethumadhavan <[log in to unmask]>

Workshop and Tutorial proposals are solicited for ISCA-36 in Austin,
Texas. Workshops and Tutorials will be held June 20-21, 2009.

Austin offers a dynamic environment with numerous universities,
research institutes, companies, and lively night life. We expect very
high attendance.

Please send workshop and tutorial proposals to Luis Ceze (luisceze AT
cs dot washington dot edu) and Carole Dulong (caroled AT google dot
com). Also, we encourage organizers to get in touch with us earlier than
the deadline, as plans develop.

Deadline for proposals is January 9, 2009. We will notify organizers  
by January 20, 2009.

For workshops, please include in your proposal:
  * title of the workshop
  * organizers and their affiliations
  * sample call for papers, including the workshop's main topics
  * expected duration of the workshop; i.e., 1/2 day, full day, or 2 days
  * if the workshop was previously held, the number of publish papers
    and attendees at the last workshop

For tutorials, include:
  * title of the tutorial
  * organizers, presenters, their affiliations, and short bios
  * abstract of the tutorial
  * a list of topics to be covered and some of their related bibliography
  * expected duration of the tutorial; i.e., 1/2 day, full day, or 2 days
  * if the tutorial was previously held, the location (i.e., which
    conference), date, and number of attendees at the last tutorial

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* CFP: PACT 2009
http://pact09.renci.org
Submitted by Mohamed Zahran <[log in to unmask]>

Parallel Architectures and Compilation Techniques 2009 (PACT-2009)
Raleigh, North Carolina, September 12-16, 2009
http://pact09.renci.org

PACT is a multi-disciplinary conference that brings together
researchers fr= om the hardware and software areas to present
ground-breaking research related to parallel systems ranging across
instruction-level parallelism, thread-level parallelism,
multiprocessor parallelism and large scale systems.  PACT solicits
novel, unpublished papers on a broad range of topics that include, but
are not limited to, the following:

Parallel architectures and computational models
Compilers and tools for parallel computer systems
Multicore, multithreaded, superscalar, and VLIW architectures
Support for concurrency correctness in hardware and software
Compiler/hardware support for managing memory hierarchies
Hardware and software support for power/heat-aware parallel computing
Parallel accelerators and reconfigurable computing
Dynamic translation and optimization for parallel systems
I/O issues in parallel computing and their relation to applications
Parallel programming languages, algorithms and applications
Middleware and run-time system support for parallel computing
Reliability and fault tolerance for parallel systems
Modeling and simulation of parallel systems and applications
Parallel applications and experimental systems studies
Non-traditional parallel computing systems topics

Important dates:

Abstract submission: Friday March 20, 2009
Full paper submission: Friday March 27, 2009
Tutorial/Workshop submission: Friday March 27, 2009
Author Notification: May 22, 2009
Final paper due: June 26, 2009
Conference: Saturday to Wednesday, September 12-16, 2009

Information for Authors:

Detailed information for electronic submission will be posted on the
PACT 2009 Web site (http://pact09.renci.org/).  The abstract
submission includes a description (100-300 words) of the paper and an
indication of the key topics of the paper.  Your paper should be
formatted in PDF format for letter-size paper.  Submissions must be
viewable by Adobe Acrobat Reader (version 7.0 or higher).  Your
submission may not exceed 10 pages of conference two column paper
format using 10pt fonts; an appropriate LaTeX style sheet is available
from the web site listed above.  The program chairs will summarily
return submissions exceeding the page limit.

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* Deadline Extension for the SMART'09
http://www.hipeac.net/smart-workshop.html
Submitted by Grigori Fursin <[log in to unmask]>

DEADLINE EXTENDED UNTIL NOVEMBER 21, 2008

                              CALL FOR PAPERS

                              3rd Workshop on
                 Statistical and Machine learning approaches                  
                       to ARchitecture and compilaTion
                                (SMART'09)

                  http://www.hipeac.net/smart-workshop.html

                     January 25, 2009, Paphos, Cyprus

                  (co-located with HiPEAC 2009 Conference)

                     **** NEW PANEL INFORMATION ****
    Can machine learning help to solve the multicore code generation issues?

                     **** NEW PUBLICATION INFORMATION ****
     Selected papers will be considered for publication in a special issue 
            of the International Journal of Parallel Programming.

The rapid rate of architectural change and the large diversity 
of architecture features has made it increasingly difficult 
for compiler writers to keep pace with microprocessor evolution. 
This problem has been compounded by the introduction of multicores.  
Thus, compiler writers have an intractably complex problem to solve. 
A similar situation arises in processor design where new approaches 
are needed to help computer architects make the best use of new underlying 
technologies and to design systems well adapted to futureapplication domains.

Recent studies have shown the great potential of statistical machine
learning and search strategies for compilation and machine design. 
The purpose of this workshop is to help consolidate and advance the state 
of the art in this emerging area of research. The workshop is a forum 
for the presentation of recent developments in compiler techniques 
and machine design methodologies based on space exploration 
and statistical machine learning approaches with the objective 
of improving performance, parallelism, scalability, and adaptability.

Topics of interest include (but are not limited to):

Machine Learning, Statistical Approaches, or Search applied to

* Feedback-Directed Compilation 
* Auto-tuning Programs + Language Extensions
* Library Generators
* Iterative Compilation 
* Dynamic Compilation/Adaptive Execution 
* Parallel Compiler Optimizations 
* Low-power Optimizations 
* Simulation 
* Performance Models 
* Adaptive Processor and System Architecture 
* Design Space Exploration 
* Other Topics relevant to Intelligent and Adaptive Compilers/Architectures

**** Paper Submission Guidelines ****
                     
Paper length - maximum 15 pages. Papers must be submitted in the PDF
(preferably) or postscript formats using the workshop submission website:
http://unidapt.org/dissemination/workshops/smart09

We suggest to use LNCS LaTeX templates that can be found at 
http://www.springeronline.com/lncs (go to "For Authors" 
and then "Information for LNCS Editors/Authors").

An informal collection of the papers to be presented will be distributed at
the workshop. All accepted papers will appear on the workshop website.

****  Important Dates ****

Final deadline for submission:  November 21, 2008
Decision notification:          December 19, 2008
Workshop:	                January 25, 2009

Program Chair:
 David Padua, University of Illinois at Urbana-Champaign, USA

Organizers:
 Grigori Fursin, INRIA Saclay, France
 John Cavazos, University of Delaware, USA

Program Committee:
 Saman Amarasinghe, MIT, USA
 Francois Bodin, CAPS Enterprise, France
 Calin Cascaval, IBM T.J. Watson Research Center, USA
 John Cavazos, University of Delaware, USA
 Franz Franchetti, Carnegie Mellon University, USA
 Ari Freund, IBM Haifa Research Lab, Israel
 Grigori Fursin, INRIA Saclay, France
 Mary Hall, USC/ISI, USA
 Robert Hundt, Google, USA
 Michael O'Boyle, University of Edinburgh, UK
 David Padua, University of Illinois at Urbana-Champaign, USA
 Richard Vuduc, Georgia Institute of Technology, USA
 David Whalley, Florida State University, USA

Panel: Can machine learning help to solve the multicore code generation issues?
 Chair:
  Francois Bodin, CAPS-Enterprise, France

 Participants: 	
  Marcelo Cintra, University of Edinburgh, UK
  Bilha Mendelson, IBM, Israel
  Lawrence Rauchwerger, Texas A&M University, USA
  Per Stenstrom, Chalmers University of Technology, Sweden

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* CFP: HPCA Workshop on 3D Integration and Interconnect-centric Architectures
Submitted by Eren Kursun <[log in to unmask]>

WORKSHOP ON 3D INTEGRATION AND INTERCONNECT-CENTRIC ARCHITECTURES

Held in conjunction with HPCA-15: International Symposium on
High-Performance Computer Architecture 
Raleigh, North Carolina, Feb 13, 2009


WORKSHOP OVERVIEW
On-chip interconnect has become a significant determinant for the
overall performance and power behavior of high performance computer
architecture in deep submicron designs. Various technology and design
solution alternatives are being actively explored to address the
interconnectivity problem including the use of: Three-dimensional
Integrated Circuits (3D-IC), RF and optical interconnect, as well as
packet-based on chip communication networks (Network-on-Chip). Among
the proposed solutions, three-dimensional integration has attracted
significant attention in recent years Ð due to the improved
interconnect characteristics that it enables. To efficiently exploit
the benefits of these technologies, design techniques and
methodologies are imperative; design space exploration at the
architectural level is also essential to fully take advantage of these
technologies to build high performance computer architectures.
The objective of the "Workshop on 3D Integration and Interconnect
Centric Architectures" is to provide a forum to explore
cross-disciplinary issues in interconnect-centric and stacked
microprocessor design for future high performance computer
architectures.

Topics of interest include, but not limited to:
- Novel interconnect technologies, including RF interconnect and
  optical interconnect
- Stacked die architectures / 3D processor design
- Novel cache hierarchies/design
- Yield and cost characteristics of 3D architectures
- Reliability issues and error tolerant design in interconnect-centric
  architectures
- Energy and thermally-efficient architectures

ORGANIZERS
Eren Kursun, IBM Research ([log in to unmask])
Yuan Xie, Penn State University ([log in to unmask])

PROGRAM COMMITTEE
Keren Bergmen, Columbia Univ.
Pradip Bose, IBM
Norman Jouppi, Hewlett-Packard
Doug Burger, Microsoft Research
Tom Conte, Georgia Tech
Chita Das, NSF and Penn State
Philip Emma, IBM
Rajeev Balasubramonian, Univ. of Utah
Jason Cong, UCLA
Tanay Tarnik, Intel
Gabriel Loh, Georgia Tech
Pol Marchal, IMEC
Xavier Vera, Intel Barcelona
Jaime Moreno, IBM
Trevor Mudge, Univ. of Michigan
Li-Shiuan Peh, Princeton
Glenn Reinman, UCLA
Li Shang, Corolado University

IMPORTANT DEADLINES
* Paper submission: December 15, 2008
* Acceptance notification: January 15, 2009
* Final version due by: January 30, 2009

SUBMISSION
All papers must be submitted electronically. Submissions are limited
to 6 pages (up to 10 pages) in the double column proceedings format
(with 10-point font size). The intent of the workshop is to encourage
the vigorous and unfettered discussion of the latest ideas in the
field,and it aims at fostering a high level of professional
interaction. Accepted papers can still be submitted to other
conferences and journals. Submission must be in pdf.

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