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Subject:
From:
Kevin Lim <[log in to unmask]>
Reply To:
Kevin Lim <[log in to unmask]>
Date:
Thu, 3 Jul 2014 00:12:58 -0700
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This is the 1st July 2014 Digest of SIGARCH Messages (sigarch-jul14a):

 * Call for Participation: PACT 2014
http://www.pactconf.org/
Submitted by Ioana Baldini <[log in to unmask]>

 * Call for Papers: ASPLOS 2015
http://asplos15.bilkent.edu.tr
Submitted by Onur Mutlu <[log in to unmask]>

 * Call for Nominations: 2014 B. Ramakrishna Rau Award
http://awards.computer.org/
Submitted by Milagros Lovos <[log in to unmask]>

 * Call for Papers: Multi-Core and Many-Core systems for EMbedded Computing 3
http://www.pdp2015.org/specialsessions/MC3/index.html
Submitted by Amirmohammad Rahmanisane <[log in to unmask]>

 * U. Virginia announces release of VoltSpot
http://lava.cs.virginia.edu/VoltSpot/
Submitted by Kevin Skadron <[log in to unmask]>

 * Call for Papers: CENICS 2014
http://www.iaria.org/conferences2014/CENICS14.html
Submitted by Cristina Pascual <[log in to unmask]>

 * Call for Papers: IA^3 2014 - SC14 Workshop
http://cass-mt.pnnl.gov/irregularworkshop.aspx
Submitted by Antonino Tumeo <[log in to unmask]>

 * Call for Papers: CGO 2015
http://www.cgo.org
Submitted by Aaron Smith <[log in to unmask]>

 * Call for Papers: Workshop on Energy Efficient SuperComputing (E2SC)
http://hpc.pnl.gov/conf/e2sc/2014/
Submitted by Kevin J Barker <[log in to unmask]> 

 * Call for Participation: Workshop on High Performance Computational Finance
http://ewh.ieee.org/conf/whpcf
Submitted by Jose Moreira <[log in to unmask]>

 * Call for Papers: INFLOW '14
https://www.usenix.org/conference/inflow14
Submitted by Kaoutar El maghraoui <[log in to unmask]>

Please view the SIGARCH website (www.sigarch.org) for the latest postings,
to submit new posts, and for general SIGARCH information.

- Kevin Lim
Researcher, HP Labs
SIGARCH Information Director <[log in to unmask]>

* Archive: http://listserv.acm.org/scripts/wa-ACMLPX.exe?A0=SIGARCH-MEMBERS
* Web pages: http://www.sigarch.org/, http://arch-www.cs.wisc.edu
* To remove yourself from the SIGARCH mailing list:
 mail [log in to unmask] with message body: unsubscribe SIGARCH-MEMBERS

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 * Call for Participation: PACT 2014
http://www.pactconf.org/
Submitted by Ioana Baldini <[log in to unmask]>

PACT 2014 - The 23rd International Conference on Parallel
Architectures and Compilation Techniques

Edmonton, Alberta, Canada, August 23-27, 2014

A great technical program for PACT 2014 is now available at:

http://www.pactconf.org/program.php

Early Bird Registration deadline is July 15 2014:

http://www.pactconf.org/registration.php

We hope that you will join us at PACT 2014.

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 * Call for Papers: ASPLOS 2015
http://asplos15.bilkent.edu.tr
Submitted by Onur Mutlu <[log in to unmask]>

20th International Conference on Architectural Support for Programming
Languages and Operating Systems

Istanbul, Turkey, March 14-18, 2015

Abstracts Due:     July 31, 2014
Full Papers Due:   August 7, 2014    

ASPLOS is the premier forum for multidisciplinary systems research
spanning computer architecture and hardware, programming languages and
compilers, operating systems and networking, as well as applications
and user interfaces. The 2015 conference will be held in Istanbul,
Turkey, a city where two continents meet on the blue waters of the
Bosphorus to offer an abundance of unique natural, historical,
cultural, and culinary experiences.

Like its predecessors, ASPLOS 2015 invites papers on ground-breaking
research at the intersection of at least two ASPLOS disciplines:
architecture, programming languages, operating systems, and related
areas. Non-traditional topics are especially encouraged. The
importance of cross-cutting research continues to grow as we grapple
with the end of Dennard scaling, the explosion of big data, scales
ranging from ultra-low power wearable devices to exascale parallel and
cloud computers, the need for sustainability, and increasingly
human-centered applications. ASPLOS embraces systems research that
directly targets these new problems in innovative ways. The research
may target diverse goals such as performance, energy and thermal
efficiency, resiliency, security, and sustainability. The review
process will be sensitive to the challenges of multidisciplinary work
in emerging areas.

Areas of interest include, but are not limited to: 
- Emerging platforms at all scales, from embedded to cloud
- Heterogeneous multicore architectures and accelerators
- Systems for enabling parallelism at an extreme scale
- Non-traditional computing systems
- Systems that address social, educational, and environmental
  challenges
- Programming models and compilation for existing and emerging
  platforms
- Managing, storing, and computing on big data
- Virtualization
- Memory and storage technologies and architectures
- Power, energy, and thermal management
- Security, reliability, and availability
- Verification and testing, and their impact on design

Papers should be submitted for double-blind review following the
submission guidelines available at the conference website -
http://asplos15.bilkent.edu.tr

Important dates:
Abstracts Due           July 31, 2014
Full Papers Due         Aug 7, 2014    
Author Response Period  Oct 20-22, 2014
Notification            Nov 10, 2014
Final Copy Deadline     Jan 14, 2015*

*Proceedings will be available in the ACM DL up to two weeks prior to
 the conference

General Co-Chairs:     
Kemal Ebcioglu, Global Supercomputing Corporation                         
Ozcan Ozturk, Bilkent University

Program Chair:         
Sandhya Dwarkadas,  University of Rochester

Program Committee:
Rajeev Balasubramonian, U. Utah / HP Labs
Andrew Baumann, Microsoft
Ricardo Bianchini, Rutgers U. / Microsoft
Hans Boehm, Google
John Carter, IBM Research
Calin Cascaval, Qualcomm
Yunji Chen, ICT, Chinese Academy of Sciences
Andrew Chien, U. Chicago / Argonne
Alan Cox, Rice U.
John Criswell, U. Rochester
Angela Demke, Brown U. Toronto
Peter Druschel, Max Planck Inst. for Software Systems (MPI-SWS)
Sandhya Dwarkadas, U. Rochester (chair)
Jason Flinn, U. Michigan
Antonio Gonzalez, UPC Barcelona
R. Govindarajan, IISc, India
Dan Grossman, U. Washington
Boris Grot, U. Edinburgh
Erik Hagersten, Uppsala U. 
Mary Hall, U. Utah
Kim Hazelwood, Google
Gernot Heiser, NICTA / UNSW, Australia
Hillery Hunter, IBM Research
Alvin Lebeck, Duke U.
David Meisner, Facebook
Jason Nieh, Columbia U.
Mark Oskin, U. Washington
Steve Reinhardt, AMD
Jennifer Sartor, Ghent U.
Xipeng Shen, College of William and Mary
Tatiana Shpeisman, Intel
Asia Slowinska, Vrije U. Amsterdam
Serdar Tasiran, Koc U., Turkey
Dan Tsafrir, Technion
Jeffrey Vetter, Oak Ridge National Lab / Georgia Tech.
Yuanyuan Zhou, UC San Diego

Publicity Chairs: 
Onur Mutlu, Carnegie Mellon University
Engin Ipek, University of Rochester
Atakan Dogan, Anadolu University

Registration Chair: 
Ulya Karpuzcu, University of Minnesota, Twin Cities

Finance Chair: 
Smail Niar, University of Valenciennes

Industry Chairs: 
Emre Ozer, ARM
Bugra Gedik, Bilkent University

Workshop Chairs: 
Alper Buyuktosunoglu, IBM
Augusto Vega, IBM
Haluk Topcuoglu, Marmara University

Publication Chair: 
Seda Ogrenci Memik, Northwestern University

Poster/Lightning Session Chair: 
Arrvindh Shriraman, Simon Fraser University

Local Arrangements Chair: 
Alper Sen, Bogazici University

Travel Grant Chair: 
Suleyman Tosun, Ankara University

Web Chair: 
Oguz Ergin, TOBB University

Tutorial Chairs: 
Osman Unsal, Barcelona Supercomputing Center
Serdar Tasiran, Koc University

Student Advocates: 
Gurhan Kucuk, Yeditepe University

Steering Committee:
Sarita Adve, UIUC
Rajeev Balasubramonian, U. Utah
Ras Bodik, UC Berkeley
Doug Burger, Microsoft
George Candea, EPFL
Al Davis, U. Utah
Jeremy Gibbons, Oxford University
Vivek Sarkar, Rice University
David Wood, U. Wisconsin

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 * Call for Nominations: 2014 B. Ramakrishna Rau Award
http://awards.computer.org/
Submitted by Milagros Lovos <[log in to unmask]>

Nomination deadline is 1 July 2014

Nomination site:  http://awards.computer.org/

ELIGIBILITY: The candidate will have made an outstanding, innovative
contribution or contributions to microarchitecture, use  of novel
microarchitectural techniques or compiler/architecture interfacing.  It is
hoped, but not required, that the winner will have also contributed to the
computer microarchitecture community through teaching, mentoring, or
community service. This award requires 3 endorsements.

AWARD: Certificate and a $2,000 honorarium.

PRESENTATION: Presented at the ACM/IEEE International Symposium on
Microarchitecture. - MICRO 47 <http://www.microarch.org/micro47/> - December
13-17, 2014 - Cambridge, UK

NOMINATION SUBMISSION:  Nominations are being accepted electronically:
http://www.computer.org/portal/web/awards/Rau

PAST RECIPIENT: Kemal Ebcioglu, President, Global Supercomputing
Corporation

"For contributions to VLIW, instruction-level-parallelism, binary
translation,Java performance, and service to the community."

CONTACT US: Send any award related questions to [log in to unmask]

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 * Call for Papers: Multi-Core and Many-Core systems for EMbedded Computing 3
http://www.pdp2015.org/specialsessions/MC3/index.html
Submitted by Amirmohammad Rahmanisane <[log in to unmask]>

Multi-Core and Many-Core systems for EMbedded Computing (MC) 3

Special session in 23rd Euromicro International Conference on
Parallel, Distributed, and Network-Based Processing (PDP 2015)

4-6 March 2015, Turku, Finland

This special session addresses all aspects of multi-core and many-core
embedded systems design. It presents new ideas in the multi-core field
such as theory and modeling, scalable and fault tolerant design
approaches and frameworks, algorithms, software, tools and
applications, analysis and comparison, design techniques and emerging
implementations.
The proceedings of the special session will be published together with
the proceedings of PDP 2015 by the IEEE Computer Society, which are
available worldwide through the IEEE Xplore Digital Library. An
extended version of the best papers of the MC3 be invited to submit
extended article versions to one of the ISI-indexed high-quality
journals.

Authors are invited to submit high quality papers representing
original work from both the academia and industry in (but not limited
to) the following topics:


* Design space exploration and design methodology for embedded
  multi-core and many-core systems

* Specification and Formal modeling of embedded multi-core and
  many-core systems

* Multi-core/many-core embedded system design challenges

* Parallel programming and software for embedded multi-core and
  many-core systems

* Memory management

* 3D architectures, integration and synthesis for embedded multi-core
  and many-core systems

* On-chip communication architectures and networks-on-chip for embedded systems

* Heterogeneous multi-core and many-core architectures

* Hardware/software co-design

* Simulation, validation and verification

* Test and Fault Tolerance

* QoS management and performance analysis

* Multi-core and many-core cyber-physical systems

* Programming languages and compilers

* Thermal-, energy-, and power-aware architectures

* Monitoring and reconfiguration

* System prototyping

* Industrial practices and case studies

* IMPORTANT DATES
Important Dates

Deadline for paper submission: 25th August 2014
Acceptance notification: 25th October 2014
Camera ready paper due: 10th November 2014

Special session chairs:


* Hannu Tenhunen (Royal Institute of Technology (KTH), Sweden)

* Axel Jantsch (Royal Institute of Technology (KTH), Sweden)

* Pasi Liljeberg (University of Turku, Finland)

* Amir-Mohammad Rahmani  (University of Turku, Finland)

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 * U. Virginia announces release of VoltSpot
http://lava.cs.virginia.edu/VoltSpot/
Submitted by Kevin Skadron <[log in to unmask]>

We are delighted to announce the official release for VoltSpot, a
pre-RTL microprocessor power delivery network (PDN) model, including
C4 bumps.

The difficulty of delivering sufficient current and stable voltage to
active devices is becoming more challenging with shrinking feature
sizes and lower voltages, adding yet another physical constraint on
performance scaling. To enable cross-layer power-delivery design and
optimization, we developed VoltSpot for architecture-level evaluation
of PDN noise and reliability. With a fine-grained on-chip model,
VoltSpot is capable of capturing the relationship between PDN design
details (e.g., C4 pad count and placement, metal layer geometry,
on-chip decoupling capacitor distribution, etc.) and supply-voltage
noise. It shares the same chip floorplan and power trace interface
with HotSpot and therefore can be easily integrated with most
power-performance simulators such as McPAT and Gem5. VoltSpot provides
a versatile platform for investigating the spatial and temporal
locality of supply voltage noise, evaluating design- and run-time
noise mitigation techniques, and estimating lifetime-reliability
problems such as electromigration (EM).  VoltSpot currently only
supports conventional, 2D designs and off-chip voltage regulators, but
extensions for 3D chips and support for on-chip voltage regulators are
coming soon.

To download VoltSpot, please visit our website:
http://lava.cs.virginia.edu/VoltSpot/

VoltSpot and HotSpot use the same floorplan and power modeling
methodology, and it appears that these two items are the most common
sources of questions for HotSpot. Support for VoltSpot will therefore
take place with the HotSpot mailing list. We also hope that this will
support joint exploration of thermal and voltage management.

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 * Call for Papers: CENICS 2014
http://www.iaria.org/conferences2014/CENICS14.html
Submitted by Cristina Pascual <[log in to unmask]>

CENICS 2014, The Seventh International Conference on Advances in
Circuits, Electronics and Micro-electronics
November 16 - 20, 2014 - Lisbon, Portugal

General page: http://www.iaria.org/conferences2014/CENICS14.html

Call for Papers: http://www.iaria.org/conferences2014/CfPCENICS14.html

Submission page: http://www.iaria.org/conferences2014/SubmitCENICS14.html

Contributions:
 - regular papers
 - short papers (work in progress)
 - posters
 - ideas
 - presentations
 - demos
 - doctoral forum submissions

Proposals for:
 - symposia
 - workshops

Submission deadline: July 16, 2014

Sponsored by IARIA, www.iaria.org
 Extended versions of selected papers will be published in IARIA
 Journals: http://www.iariajournals.org
 Print proceedings will be available via Curran Associates, Inc.:
 http://www.proceedings.com/9769.html
 Articles will be archived in the free access ThinkMind Digital
 Library: http://www.thinkmind.org

The topics suggested by the conference can be discussed in term of
concepts, state of the art, research, standards, implementations,
running experiments, applications, and industrial case
studies. Authors are invited to submit complete unpublished papers,
which are not under review in any other conference or journal in the
following, but not limited to, topic areas.

All tracks are open to both research and industry contributions, in
terms of Regular papers, Posters, Work in progress,
Technical/marketing/business presentations, Demos, Tutorials, and
Panels.

Before submission, please check and comply with the Editorial rules:
http://www.iaria.org/editorialrules.html

CENICS 2014 Topics (topics and submission details: see CfP on the site)

Semiconductors and applications
     Special semiconductors; Tunable bandgap semiconductors;
     Piezoelectricity; Polarization; Breakdown voltage;
     Superconductivity; Ferromagnetism; Biocompatibility; Chemical and
     thermal stability; Power amplification at very high frequencies;
     High temperature electronics; LEDs and lasers; Photodetectors;
     Transistors; Piezoelectric filters

Design, models and languages
     Languages and models for specification and design of hardware;
     Robust, reliable and/or safe embedded electronics;
     Circuits/hardware description languages; Standards related to
     design languages; Processor and memory design; Embedded system
     design; VHDL-related standards; Electronic circuits modelling;
     Automatic generation of models; Quantitative analysis of models;
     Distributed CAD systems; Collaborative design based on Internet
     and WWW; Electronic systems design based on WWW; System- and
     high-level synthesis, HW/SW codesign

Signal processing circuits
     Signal processing; High-speed signal processing; Multi-scale
     signal processing and imaging; Asynchronous circuits and systems;
     High frequency processing; Power and signal amplifiers; Parallel
     processing circuits; Equalization processing; Compression,
     transcoding, and applied signal processing

Arithmetic computational circuits
     Operational arithmetic circuits; Basic arithmetic operations;
     Modular operations; Decimal-floating point operations;
     Multiple-precision operations; Squaring and exponentiation;
     Polynomial evaluations; Periodic functions; Operational
     approximations; Parallel decimal operations

Microelectronics
     Components and circuits for communications; HMIC and MMIC design;
     Micro-electronics; Nano-electronics; Lasers and mini-lasers;
     Miniature devices; Low power electronics; Nano-scale electronics
     materials

Electronics technologies
     Organic optoelectronic; Implantable electronics; Wearable
     electronics; Low power electronics; Electronic microarray
     technology and applications; RF and Microwave

Special circuits
     Programmable circuits; Design of reconfigurable micro-chips; VLSI
     circuits design; Low-noise circuits; Digital modulators;
     Micro-sensors; Micro-antennas; Thermal circuits; Reconfigurable
     circuits; Dynamically reconfigurable processors; Oscillators;
     VCOs and phased-array transmitters

Consumer electronics
     Home-oriented electronics; Biometric circuits; Home gateway; Home
     theater circuitry; Game systems; Interactive and directed
     programming electronics; Advanced DVD and CD; Interactive and
     directed programming electronics

Application-oriented electronics
     Navigation electronics; Industrial electronics; Automotive
     electronics; Application-oriented electronics; Telemedicine and
     eHealth electronics; Biochip design for health science
     applications; Bio-systems and miniature instruments; Biosensors
     and biosensor networks; Industrial measurement electronics;
     Industrial control electronics; Energy distribution electronics;
     Energy saving and conversion circuits; Indoor and outdoor light
     control systems; Power electronics; Avionics electronics;
     Railways electronics; Vehicular electronics; Embedded
     electronics; Process industry electronics

 Committee: http://www.iaria.org/conferences2014/ComCENICS14.html

CENICS Advisory Chairs
 Vladimir Privman, Clarkson University - Potsdam, USA
 Sergey Y. Yurish, Technical University of Catalonia (UPC-Barcelona), Spain
 Martin Horauer, University of Applied Sciences Technikum Wien, Austria
 Adrian Muscat, University of Malta, Malta

CENICS 2014 Research/Industry Chairs
 Ravi M. Yadahalli, PES Institute of Technology & Management - Karnataka, India

CENICS 2014 Industry Liaison Chairs
 Falk Salewski, Muenster University of Applied Sciences, Germany

CENICS 2014 Special Area Chairs

Formalisms
 Peeter Ellervee, Tallinn University of Technology, Estonia

Application-oriented
 Josu Etxaniz Maranon, University of the Basque Country / Universidad
 del Pais Vasco / Euskal Herriko Unibertsitatea - Bilbao, Spain

Sensors
 Yulong Zhao, Xi'an Jiaotong University, China

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 * Call for Papers: IA^3 2014 - SC14 Workshop
http://cass-mt.pnnl.gov/irregularworkshop.aspx
Submitted by Antonino Tumeo <[log in to unmask]>
 
IA^3 2014 - SC14 Workshop on Irregular Applications: Architectures and
Algorithms

New Orleans, LA
November 16, 2014
Held in conjunction with SC14 (http://sc14.supercomputing.org)
Held in cooperation with ACM SIGHPC (http://www.sighpc.org)

THEME
Irregular applications span a broad range of applications with
unpredictable memory access patterns, control structures, and/or
network transfers. They typically use pointer-based data structures
such as graphs and trees, often present fine-grained synchronization
and communication, and generally operate on very large data sets. They
have a significant degree of latent parallelism, which however is
difficult to exploit due to their complex behavior. Current high
performance architectures rely on data locality and regular
computation to tolerate access latencies, and often do not cope well
with the requirements of these applications. Furthermore, irregular
applications are difficult to scale on current supercomputing
machines, due to their limits in fine-grained synchronization and
small data transfers.

Irregular applications pertain both to well established and emerging
fields, such as social network analysis, bioinformatics, semantic
graph databases, bioinformatics, Computer Aided Design (CAD) and
computer security. Many of these application areas also process
massive sets of unstructured data, which keep growing
exponentially. Addressing the issues of irregular applications on
current and future architectures will become critical to solve the
scientific challenges of the next few years.

This workshop seeks to explore solutions for supporting efficient
execution of irregular applications in the form of new features at the
level of the micro- and system-architecture, network, languages and
libraries, runtimes, compilers, analysis, algorithms.  Topics of
interest, of both theoretical and practical significance, include but
are not limited to:

* Micro- and System-architectures
* Network and memory architectures
* Heterogeneous, custom and emerging architectures (GPUs, FPGAs,
  multi- and many-cores)
* Modeling, simulation and evaluation of architectures
* Innovative algorithmic techniques
* Parallelization techniques and data structures
* Approaches for managing massive unstructured datasets
* Languages and programming models
* Library and runtime support
* Compiler and analysis techniques
* Graph databases

Besides regular papers, papers describing work-in-progress or
incomplete but sound, innovative ideas related to the workshop theme
are also encouraged. We solicit both 8-page regular papers and 4-page
position papers.

SUBMISSIONS
Submission site: https://www.easychair.org/conferences/?conf=ia32014

All submissions should be in double-column, single-spaced letter
format, using 9-point size fonts, with at least one-inch margins on
each side.

The proceedings of the workshop will be published in cooperation with
ACM SIGHPC, so authors can use the ACM official templates, available
at http://www.acm.org/sigs/publications/proceedings-templates, to
simplify the editing process.

Submitted manuscripts may not exceed eight pages in length for regular
papers and four pages for position papers including figures, tables
and references.

For any question, please contact the organizers.

IMPORTANT DATES
Abstract submission:  25 August 2014
Full or position paper submission: 1 September 2014
Notification of acceptance:  3 October 2014
Camera-ready papers: 10 October 2014
Workshop: 16 November 2014

ORGANIZERS
Antonino Tumeo, Pacific Northwest National Laboratory, [log in to unmask]
John Feo, Pacific Northwest National Laboratory, [log in to unmask]
Oreste Villa, NVIDIA Research, [log in to unmask]

PROGRAM COMMITTEE
Keren Bergman, Columbia University, USA
Jay Brockman, University of Notre Dame, USA
David Brooks, Harvard University, USA
Bryan Catanzaro, NVIDIA, USA
Daniel Chavarria, Pacific Northwest National Laboratory, USA
Srini Devadas, Massachusetts Institute of Technology, USA
Georgi Gaydadjiev, Chalmers University, SWE
Maya Gokhale, Lawrence Livermore National Laboratory, USA
Martha Kim, Columbia University, USA
John Leidel, Texas Tech University, USA
Kamesh Madduri, The Pennsylvania State University, USA
Alessandro Morari, Pacific Northwest National Laboratory, USA
Timothy Mattson, Intel, USA
Richard Murphy, Micron Technology, Inc., USA
Walid Najjar, University of California Riverside, USA
Kunle Olukotun, Stanford University, USA
Gianluca Palermo, Politecnico di Milano, ITA
Fabrizio Petrini, IBM TJ Watson, USA
Vivek Sarkar, Rice University, USA
Erik Saule, University of North Carolina at Charlotte, USA
John Shalf, Lawrence Berkeley National Laboratory, USA
Simone Secchi, ARM, UK
Michela Taufer, University of Delaware, USA
Pedro Trancoso, University of Cyprus, CYP
Mateo Valero, Barcelona Supercomputing Center, SPA

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 * Call for Papers: CGO 2015
http://www.cgo.org
Submitted by Aaron Smith <[log in to unmask]>

2015 IEEE/ACM International Symposium on Code Generation and Optimization
February 2015 - San Francisco Bay Area
http://cgo.org/cgo2015/

The International Symposium on Code Generation and Optimization (CGO) provides
a premier venue to bring together researchers and practitioners working at the
interface of hardware and software on a wide range of optimization and code
generation techniques and related issues. The conference spans the spectrum
from purely static to fully dynamic approaches, including techniques ranging
from pure software-based methods to architectural features and support.

Original contributions are solicited on, but not limited to, the following
topics:

Code Generation and Optimization
- Efficient execution of dynamically typed and higher-level languages
- Optimization and code generation for emerging programming models, platforms
- Optimizations for energy efficiency
- Profile-guided, feedback-directed, and machine learning based optimization
- Compiler abstractions and intermediate representations

Static and Dynamic Analysis
- Profiling and instrumentation for power, memory, throughput or latency
- Efficient profiling and instrumentation techniques
- Program characterization methods
- Profile-guided optimization
- Novel and efficient tools for power, performance analysis, debugging and
testing

Optimization for Parallelism
- Runtime systems for parallelism & heterogeneity
- Optimizations for heterogeneous or specialized parallel targets, e.g. GPUs
- Compiler-driven data distribution and synchronization
- Thread extraction

OS, Architecture and Runtime Support
- Architectural support for improved profiling, optimization and code
generation
- Integrated system design (HW/OS/VM/SW)
- Memory management and garbage collection

Security and Reliability
- Code analysis and transformations to address security or reliability concerns

Practical Experience
- Deployed dynamic and static compiler and runtime systems for general purpose,
embedded system and Cloud/HPC platforms

Applications of above in emerging technology areas, such as
- Web programming environments, application runtimes, optimizations
- SOCs, heterogeneous platforms hardware/software co-design, analysis and
optimization

CGO 2015 is co-located with HPCA 2015 and PPoPP 2015 this year. Authors should
carefully consider the difference in focus of the conferences when deciding
where to submit a paper.

CGO will make the proceedings freely available via the ACM DL platform for up
to two weeks before and two weeks after the event. This option will facilitate
easy access to the proceedings by conference attendees, and it will also enable
the community at large to experience the excitement of learning about the
latest developments being presented in the period surrounding the event itself.

Important Dates
Abstract Submission: August 29, 2014
Paper Submission: September 5, 2014
Author Response Period: October 21-23, 2014
Notification to Authors: November 3, 2014

General Chairs
Kunle Olukotun, Stanford University
Aaron Smith, Microsoft Research

Program Chairs
Robert Hundt, Google
Jason Mars, University of Michigan

Program Committee
Saman Amarsinghe, MIT
Derek Bruening, Google
Simone Campanoni, Harvard
Mike Carbin, MIT
John Cavazos, U. of Delaware
Albert Cohen, INRIA
Jack Davidson, UVA
Gregory Diamos, NVidia
Evelyn Duesterwald, IBM
Xiaobing Feng, ICT Chinese Academy
Mike Ferdman, Stony Brook University
Ravi Iyer, Intel
Alexandra Jimborean, Uppsala University
Naveen Kumar, Google
Calvin Lin, UT Austin
Scott Mahlke, Michigan
Kathryn S McKinley, Microsoft
Abdullah Muzahid, UT San Antonio
Chris J Newburn, Intel
Michael O'Boyle, Edinburgh
David Padua, UIUC
Depei Qian, Xi'an Jiaotong University
Lawrence Rauchwerger, Texas A&M University
Vijay Janapa Reddi, The University of Texas at Austin
Behnam Robatmili, Qualcomm Research
Norm Rubin, NVidia
Jennifer Sartor, Ghent
Xipeng Shen, William and Mary
Lingjia Tang, Michigan
Mike Taylor, UCSD
Mohit Tiwari, UT Austin
James M. Tuck, NCSU
Cheng Wang, Intel Labs
Chenggang Wu, Chinese Academy of Sciences
Jingyue Wu, Google
Eddy Zhang, Rutgers
Ben Zorn, Microsoft Research

Workshop and Tutorials Chair
Christophe Dubach, University of Edinburgh

Finance Chair
Vijay Janapa Reddi, The University of Texas at Austin

Local Chairs
Jose Renau, University of California, Santa Cruz
Behnam Robatmili, Qualcomm Research

Publications Chair
Fabrice Rastello, INRIA

Students Chair
Jennifer Sartor, Ghent University

Sponsors Chair
Ben Zorn, Microsoft Research

Registration Chair
Lingjia Tang, University of Michigan

Submission Chairs
Michael Laurenzano, University of Michigan
Yunqi Zhang, University of Michigan

Web Chair
Mehrzad Samadi, University of Michigan

Steering Committee
Kim Hazelwood, Google
Robert Hundt, Google
Scott Mahlke, University of Michigan
Kathryn S McKinley, Microsoft
Kunle Olukotun, Stanford University
Vijay Janapa Reddi, The University of Texas at Austin
Olivier Temam, INRIA (Chair)

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 * Call for Papers: Workshop on Energy Efficient SuperComputing (E2SC)
http://hpc.pnl.gov/conf/e2sc/2014/
Submitted by Kevin J Barker <[log in to unmask]> 
 
2nd International Workshop on Energy Efficient SuperComputing (E2SC)
Held in conjunction with SC'14, New Orleans, Louisiana, USA
November 16th-21st 2014

Description
-----------
With Exascale systems on the horizon, we will be ushering in an era with power 
and energy consumption as the primary concerns for scalable computing. To 
achieve viable high performance, revolutionary methods are required with a 
stronger integration among hardware features, system software and applications. 
Equally important are the capabilities for fine-grained spatial and temporal 
measurement and control to facilitate energy efficient computing across 
all layers. Current approaches for energy efficient computing rely heavily on 
power efficient hardware in isolation. However, it is pivotal for hardware to 
expose mechanisms for energy efficiency to optimize power and energy 
consumption for various workloads and to reduce data motion, a major component
of energy use. At the same time, high fidelity measurement techniques, 
typically ignored in data-center level measurement, are of high importance 
for scalable and energy efficient inter-play in different layers of 
application, system software and hardware.

This workshop seeks to address the important energy efficiency aspects in the 
HPC community that have not been previously addressed by aspects covered in 
the data center or cloud computing communities. Emphasis is given to the 
applications view related to significant energy efficiency improvements and 
to the required hardware/software stack that must include necessary power and 
performance measurement and analysis harnesses.  

Current tools are often limited by hardware capabilities and their lack of 
information about the characteristics of a given workload/application. In the 
same manner, hardware techniques, like dynamic voltage frequency scaling, are 
often limited by their granularity (very coarse power management) or by their 
scope (a very limited system view). More rapid realization of energy savings 
will require significant increases in measurement resolution and optimization 
techniques.  Moreover, the interplay between performance, power and 
reliability add another layer of complexity to this already difficult group 
of challenges.


Workshop Focus
--------------
We encourage submissions in the following areas:

- Tools for analyzing power and energy with different granularities and
  scope from hardware (e.g., component, core, node, rack, system) or 
  software views (e.g., threads, tasks, processes, etc.) or both.
- Tools and techniques for measurement, analysis, and modeling of thermal
  effects at different granularities (e.g., component, core, node, rack,
  system) for large-scale systems.
- Techniques that enable power and energy optimizations at different
  scale levels for HPC systems.
- Integration of power-aware technologies in applications and throughout
  the software stack of HPC systems.
- Characterization of current state-of-the-art HPC systems and
  applications in terms of power.
- Disruptive hardware of infrastructure technologies for energy-efficient
  supercomputing.
- Analysis of future technologies that will provide improved energy 
  consumption and management on future HPC systems.

Organizing Committee
--------------------
General Chairs:   Kirk Cameron, Virginia Tech, USA
                  Adolfy Hoisie, Pacific Northwest National Laboratory, USA
                  Darren Kerbyson, Pacific Northwest National Laboratory, USA
                  David Lowenthal, Arizona State University, USA
                  Dimitrios S. Nikolopoulos, Queen's University of Belfast, UK
                  Sudha Yalamanchili, Georgia Institute of Technology, USA
Program Chair:    Andres Marquez, Pacific Northwest National Laboratory, USA
Publicity Chair:  Kevin J. Barker, Pacific Northwest National Laboratory, USA
European Liaison: Michele Weiland, EPCC, UK
Publication Chair: Abhinav Vishnu, Pacific Northwest National Laboratory, USA
Onsite Coordination: Joseph Manzano, Pacific Northwest National Laboratory, USA


Program Committee
-----------------
Avram Bar-Cohen         DARPA-MTO, USA
Laura Carrington        San Diego Supercomputing Center, USA
Sunita Chandrasekaran   University of Houston, USA
Paul Franzon            North Carolina State University, USA
Roberto Gioiosa         Pacific Northwest National Laboratory, USA
Georg Hager             Erlangen Regional Computing Center, Germany
Karen Karavanic         Portland State University, USA
Hyesoon Kim             Georgia Institute of Technology, USA
Dong Li                 Oak Ridge National Laboratory, USA
Sheng Li                Intel, USA
Benoit Meister          Reservoir Labs, USA
Leonid Oliker           Lawrence Berkeley National Laboratory, USA
Barry Rountree          Lawrence Livermore National Laboratory, USA
Vijay Reddi             University of Texas at Austin, USA
Sameer Shende           University of Oregon, USA
Shuaiwen Leon Song      Pacific Northwest National Laboratory, USA
Eric Van Hensbergen     ARM Research, USA


Important Dates
---------------
Paper Submission        24th August 2014
Paper Notification      25th September 2014
Final Papers Due        10th October 2014


Submission Guidelines
---------------------
Papers should not exceed eight single-space pages (including figures, tables
and references) using a 12-point on 8.5x11-inch pages. Submissions will be
judged on correctness, originality, technical strength, significance,
presentation quality and appropriateness. Submitted papers should not have
appeared in or under consideration for another venue. A full peer-review
processes will be followed with each paper being reviewed by at least 3
members of the program committee. Submissions will be made through EasyChair
(http://www.easychair.org)

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 * Call for Participation: Workshop on High Performance Computational Finance
http://ewh.ieee.org/conf/whpcf
Submitted by Jose Moreira <[log in to unmask]>

WHPCF'14: Call for Participation

The Seventh Workshop on High Performance Computational Finance (WHPCF'14)
is being held in co-operation with sighpc on the 16th of November at SC'14
in New Orleans. The purpose of this workshop is to bring together
practitioners, researchers, vendors, and scholars from the complementary
fields of computational finance and high performance computing, in order
to promote an exchange of ideas, discuss future collaborations and develop
new research directions. Financial companies increasingly rely on high
performance computers to analyze high volumes of financial data,
automatically execute trades, and manage risk.

As financial market data continues to grow in volume and complexity,
computational capabilities of emerging hardware also increases. Extracting
high performance from emerging architectures requires a combination of
domain knowledge and specialized technical skills. The workshop will
explore how researchers, scholars, vendors and practitioners are
collaborating to address high performance computing research challenges.

We seek submissions that cover various aspects of computational finance.
In addition to submissions that deal with performance and programmability
challenges, theoretical analysis, algorithms, and practical experience in
computational finance, we also particularly encourage submissions that
demonstrate or result from the collaboration between financial
practitioners, and scholars, researchers, or vendors.

For 2014, we are particularly interested in submissions addressing the
following emerging topics in high performance computational finance:

-Financial analytics, including Big Data in computational finance
-Software infrastructure for high performance and high productivity
-Use of FPGAs for high frequency trading

Additional topics of interest to this workshop are listed on the workshop
webpage http://ewh.ieee.org/conf/whpcf.

==Author Instructions==

Submitted papers must be no more than 8 pages in length. The camera ready
version of accepted papers must be in ACM Proceedings format (latex users
should select Option 2). Each submission will receive at least three
reviews from the technical program committee and authors of selected
submissions will have 30 minutes to present their work at the workshop.
Papers should be submitted in electronic form to [log in to unmask]

==Important Dates==

Submission deadline: August 22nd, 11:59 EST
Author notification: September 19th
Final version due: October 3rd

==Program Committee==

Claudio Albanese, Global Valuation
John Ashley, NVIDIA Corporation
David Cohen, EMC
Patrick Flannery, May Street
Dhiraj Kalamkar, Intel Corporation
Hicham Lahlou, Xcelerit
Peter Lankford, STAC Research
Pat Miller, Jump Trading
Travis Oliphant, Continuum Analytics
Andrew Rau-Chaplin, Dalhousie University
Mohammad Zubair, Old Dominion University

==Steering Committee==

David Daly, MongoDB
Matthew Dixon, University of San Francisco
Jose Moreira, IBM Thomas J. Watson Research Center

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 * Call for Papers: INFLOW '14
https://www.usenix.org/conference/inflow14
Submitted by Kaoutar El maghraoui <[log in to unmask]>

Interactions of NVM/Flash with Operating-Systems and Workloads
OSDI'14 Workshop,   Oct 5, 2014  at Broomfield, CO, USA.

Submission Date: July 21st, 2014      Acceptance:   Aug 25th, 2014

The goal of INFLOW'14 is to bring together researchers and
practitioners working in systems, across the hardware/software stack,
who are interested in the cross-cutting issues of NVM/Flash
technologies, Operating Systems, and emerging Workloads.

In recent years, NVM based storage devices have been gaining
popularity as a medium of storage. Flash based SSDs in particular have
had a widespread adoption by the industry driven by the need for
greater storage performance.  NVM storage devices have dramatically
different properties than conventional hard disks. Yet, most of these
devices are still exposed to operating systems as block-level devices
similar to hard disks. There are still several fundamental research
issues to be explored on how to efficiently interface with NVM and
Flash based storage devices, and the implications of such devices in
large scale workload deployments and on emerging workloads such as
Analytics applications.

The INFLOW Workshop is an attempt to bring top researchers across the
World to exchange ideas and discuss recent innovations related to
NVM/Flash technologies and their interactions with Operating systems
and workloads, and doing this in the context of current enterprises
and consumer markets.

Checkout the CFP:
https://www.usenix.org/conference/inflow14/call-for-papers
CFP pdf version :
https://www.usenix.org/sites/default/files/inflow14_cfp_063014.pdf

Important Dates
---------------
Full paper submission due:       Tuesday    July 21st, 2014
[ DEADLINE EXTENDED ]
Notification of acceptance:        Monday     August 25th, 2014
Final papers due:                      Thursday   September 17th,
2014
Conference:                              Sunday     October 5, 2014

Topics
------
 We invite research papers from all areas of Flash SSD and its
interactions
 with operating systems and workloads.
 Major Areas of interests include, but are not limited to:

   * Operating systems support for Flash and other NVM technologies
   * New filesystem / storage software design ideas to support Flash
   * Virtualization trends for SSD storage
   * Flash SSD and NVM in Cloud Computing
   * Applications on NVM/Flash, Mobile Devices, Wearable Computing
Devices, etc.
   * Application/OS optimizations tailored for Flash storage unique
properties
   * Application/OS optimizations for other NVM technologies
   * Emerging Workloads (BigData, Analytics, Social, etc.) for
Flash/NVM
   * Workload characterization for NVM/Flash devices
   * SSD caching techniques
   * Acceleration techniques for Flash Storage and NVM technologies
   * Hybrid SSD technologies

Submission Site:    https://papers.usenix.org/hotcrp/inflow14/

Workshop Organizers and Committee:
----------------------------------
Program Co-Chairs

		Kaoutar El Maghraoui, IBM T. J. Watson Research Center
		Gokul Kandiraju, IBM T. J. Watson Research Center

Program Committee

		Nitin Agrawal, NEC Labs
		Mahesh Balakrishnan, Microsoft Research
		Philippe Bonnet, IT University of Copenhagen, Denmark
		Michele M. Franceschini, IBM T. J. Watson Research Center
		K. Gopinath, Indian Institute of Science, India
		Haryadi S. Gunawi, University of Chicago
		Paolo Ienne, EPFL
		Jihong Kim, Seoul National University, Korea
		Carlos Maltzahn, University of California, Santa Cruz
		Arif Merchant, Google
		Sam H. Noh, Hongik University, Korea
		Alma Riska, Netapp
		Steven Swanson, University of California, San Diego
		Nisha Talagala, Fusion IO
		Bhuvan Urgaonkar, The Pennsylvania State University
		Luis Useche, VMware
		Chuliang Weng, Huawei Shannon Lab

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