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Subject:
From:
Kevin Lim <[log in to unmask]>
Reply To:
Kevin Lim <[log in to unmask]>
Date:
Mon, 25 Feb 2013 17:19:34 -0800
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This is the 2nd February 2013 Digest of SIGARCH Messages (sigarch-feb13b):

 * Call for Nominations: ACM-IEEE CS Eckert-Mauchly Award,
                         ACM SIGARCH Maurice Wilkes Award,
                         ACM SIGARCH Distinguished Service Award
http://www.sigarch.org/awards
Submitted by Kevin Lim <[log in to unmask]>

 * Call for Nominations: IEEE TCCA Young Computer Architect Award
Submitted by Ruby Lee <[log in to unmask]>

 * Call for Papers: Parallel Architectures and Compilation Techniques 2013
http://www.pactconf.org/
Submitted by Ioana Baldini <[log in to unmask]>

 * Call for Papers: ICCD 2013
http://www.iccd-conf.com/
Submitted by Rainer Buchty <[log in to unmask]>

 * Call for Papers: ICAC 2013 
https://www.usenix.org/conference/icac13
Submitted by Ming Zhao <[log in to unmask]>

 * Call for Participation: ISPASS 2013 Workshops and Tutorials
Submitted by Ioana Baldini <[log in to unmask]>

 * Call for Participation: PACT 2013 ACM Student Research Competition
https://www.easychair.org/conferences/?conf=pact2013src
Submitted by Ioana Baldini <[log in to unmask]>

 * Call for Participation: Using Queuing Theory to Model Data Center Systems
http://www.eecs.umich.edu/BigHouse/
Submitted by Thomas Wenisch <[log in to unmask]>

 * Call for Papers: ACM TACO 2.0
http://mc.manuscriptcentral.com/taco  
Submitted by Tom Conte <[log in to unmask]>

 * Call for Papers: IEEE Micro Special Issue on Dark Silicon
https://mc.manuscriptcentral.com/micro-cs
Submitted by Michael Bedford Taylor <[log in to unmask]>

 * Call for Presentations: 2nd Dark Silicon Workshop (DaSi 2013)
http://darksilicon.ucsd.edu
Submitted by Jack Sampson <[log in to unmask]>

 * Call for Papers: MCsoC-13
http://www.mcsoc-forum.org/ 
Submitted by Abderazek Ben Abdallah <[log in to unmask]>

 * Call for Papers: ICPP-EMS'2013
https://sites.google.com/site/icppems2013/home
Submitted by Kuan-Ching Li <[log in to unmask]>

Please view the SIGARCH website (www.sigarch.org) for the latest postings.

- Kevin Lim
Researcher, HP Labs
SIGARCH Information Director <[log in to unmask]>

* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.sigarch.org/
* To remove yourself from the SIGARCH mailing list:
 mail [log in to unmask] with message body: unsubscribe SIGARCH-MEMBERS

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 * Call for Nominations: ACM-IEEE CS Eckert-Mauchly Award,
                         ACM SIGARCH Maurice Wilkes Award,
                         ACM SIGARCH Distinguished Service Award
http://www.sigarch.org/awards
Submitted by Kevin Lim <[log in to unmask]>

The nomination process is open for multiple ACM SIGARCH associated
awards. These include:
* ACM-IEEE CS Eckert-Mauchly Award: Deadline March 30, 2013
http://www.sigarch.org/awards/acm-eckert-mauchly-award/

* ACM SIGARCH Maurice Wilkes Award: Deadline March 1, 2013
http://www.sigarch.org/awards/acm-sigarch-maurice-wilkes-award/

* ACM SIGARCH Distinguished Service Award: Deadline March 1, 2013
http://www.sigarch.org/awards/acm-sigarch-distinguished-service-award/

Please see the websites and the general SIGARCH award page
(http://www.sigarch.org/awards) for additional information on the
nomination processes. Past winners of all awards can also be found on
the site.

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 * Call for Nominations: IEEE TCCA Young Computer Architect Award
Submitted by Ruby Lee <[log in to unmask]>
 
The IEEE TCCA Young Computer Architect Award recognizes outstanding, 
innovative, high impact research contributions in the field of Computer 
Architecture by an individual, within 6 years of receiving his or her PhD degree.
The IEEE Computer Society administers the award.
The nominator must provide the following information to the Awards chair, Prof. 
Ruby Lee, at [log in to unmask] by March 15, 2013:
1. Name/email of person making the nomination.
2. Name/email of award candidate.
3. A statement by the nominator (maximum of 500 words) as to why the nominee 
deserves the award. The statement and supporting letters should address what 
the research contributions are, and why they are outstanding and significant.
4. CV of the candidate.
5. Names/email addresses of 2 people who the nominator has contacted to send 
supporting letters directly to the Awards chair.
The award will be presented at ISCA 2013 in Tel Aviv, Israel.

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 * Call for Papers: Parallel Architectures and Compilation Techniques 2013
http://www.pactconf.org/
Submitted by Ioana Baldini <[log in to unmask]>

PACT '13
Edinburgh, Scotland, UK
7 - 11 September 2013

PACT is a premier conference that brings together researchers from
architecture, compilers, applications and languages to present and discuss
innovative research of common interest. PACT solicits novel papers,
workshops,
tutorials and an ACM research student competition on a broad range of topics
that include, but are not limited to:

* Parallel architectures and computational models
* Compilers and tools for parallel computer systems
* Multicore, multithreaded, superscalar, and VLIW architectures
* Compiler/hardware support for hiding memory latencies
* Support for correctness in hardware and software (esp. with concurrency)
* Reconfigurable computing
* Dynamic translation and optimization
* I/O issues in parallel computing and their relation to applications
* Parallel programming languages, algorithms and applications
* Middleware and run time system support for parallel computing
* High performance application specific systems
* Applications and experimental systems studies
* Non-traditional computing systems topics

*** Important Dates for Authors, Tutorial / Workshop Organizers
*** and ACM Research Student Competitors:

*** Main Conference Papers
* Abstract Submission             11 March 2013
* Paper Submission (firm)         15 March 2013
* Rebuttal Period                 28-30 April 2013
* Author Notification             20 May 2013

*** Tutorials / Workshops:
* Workshop/Tutorial Proposals     22 March 2013

*** ACM Student Research Competition
* Abstract Submission             21 June 2013


***Author Information:

Detailed instructions for electronic submission and other important dates
will
be posted on the PACT conference web site. For additional information
regarding paper submissions, please contact the Program Chairs).

***Tutorials / Workshops:

Proposals are solicited for tutorials and workshops to be held immediately
before the conference (7 & 8 September). Proposals for Tutorials and
Workshops
are due 22th March 2013. Interested individuals are invited to contact the
Workshops/Tutorials Chairs.

* Workshop/Tutorial Proposals     22 March 2013
* Acceptance Notification         29 March 2013

***ACM Student Research Competition

PACT 2013 calls for participation in the ACM Student Research
Competition (SRC). All eligible participants are entitled to
travel grant. Winners will receive monetary prizes and others.
The expected submission deadline is 21 June 2013. Please see the
PACT web site for details.

* Abstract Submission             21 June 2013
* Acceptance Notification         12 July 2013

***Location Information:

PACT 2013 will take place at the Surgeons' Hall in Edinburgh, UK. Edinburgh
is the inspiring capital of Scotland, where centuries of history meet a
vibrant, cosmopolitan city in an unforgettable setting. Discover stunning
scenery, striking architecture, and beautiful coast and countryside in the
nearby Lothians. Edinburgh is the world's festival capital, with the
Festival
Fringe finishing just one week before PACT.
From Edinburgh, many other places are within reach of a few hours travel:
St. Andrews with its world famous golf course, Glasgow with its unique
industrial centre; or the Scottish Highlands with their rough natural
beauty.

PACT'13 Organizing Committees
----------

General Chair:
   Michael O'Boyle, U of Edinburgh

Organization Chair:
   Christian Fensch, U of Edinburgh

Program Co-Chairs:
   Andre Seznec, Inria Rennes
   Francois Bodin, Irisa/CAPS Entreprise

Finance Committee:
   Chair Timothy Jones, U of Cambridge
   Joanne Pennie, U of Edinburgh

Tutorials/Workshop Co-Chairs:
   Natalie Enright Jerger, U of Toronto
   Tom Wenisch, U of Michigan

ACM Student Research Competition Chair:
   Erik Altman, IBM

Local Arrangements Chair:
   Christophe Dubach, U of Edinburgh

Industrial Liaison Chair:
   John Cavazos, U of Delaware

Publicity Chairs:
   Americas: Ioana Baldini, IBM
   Pacific: Kei Hiraki, U of Tokyo
   China: Wenguang Chen, Tsinghua U
   India: Uday Khedker, Indian Inst. of Tech at Bombay
   Europe: Chronis Xekelakis, Intel

Publication Chair:
   Hiroshi Sasaki, Kyushu U

Web Chair:
   Emily Blem, U of Wisconsin - Madison

Submission Chair:
   Damien Hardy, U de Rennes I/IRISA

Registration Chairs:
   Vijay Nagarajan, U of Edinburgh

Student Travel Award Chair:
   TBC

Steering Committee:
----------
SangYeun Cho, Samsung/U of Pittsburgh
Michel Cosnard, INRIA
Luiz DeRose, Cray
Kemal Ebcioglu (Chair), Global Supercomputing
Jean Luc Gaudiot, UC Irvine
David Lilja, U of Minnesota
Lawrence Rauchwerger, Texas A&M U
Vivek Sarkar, Rice U
Gabriel Silberman, CA Technologies
Pen-Chung Yew, U of Minnesota

Program Committee:
----------
Aamer Jaleel, Intel
Ahmed Louri, U of Arizona
Amirali Baniasadi, U of Victoria
Ayal Zaks, Intel
Barbara Chapman, U of Houston
Ben Juurlink, Berlin U of Technology
Bilha Mendelson, IBM
Brad Beckman, AMD
Bronis R. de Supinski, LLNL
Bryan Catanzaro, NVIDIA
Cedric Bastoul, U Paris-Sud
Chita Das, Penn State
Cliff Young, D.E. Shaw Research
Damien Hardy, U de Rennes I/IRISA
David August, Princeton U
David Whalley, FSU
Emre Ozer, ARM
Eric Rotenberg, NCSU
Erik Hagerstern, Uppsala U
Evelyn Duesterwald, IBM
Federico Silla, Technical U of Valencia
Gilles Pokam, Intel
Haibo Chen, Shanghai Jiao Tong U
Jason Mars, UCSD
Jenq Kuen Lee, Natl. Tsing Hua U
John Cavazos, U of Delaware
Keshav Pingali, U of Texas at Austin
Kunle Olukotun, Stanford U
Lawrence Rauchwerger, Texas A&M U
Linda Torczon, Rice U
Marcelo Cintra, U of Edinburgh/Intel
Maria Garzaran, UIUC
Moinuddin Qureshi, Georgia Tech
Onur Mutlu, CMU
Paolo Faraboschi, HP
Per Stenstrom, Chalmers U of Technology
Qing Yang, URI
Qing Yi, UCCS
Raymond Namyst, U of Bordeaux 1
Robert Hundt, Google
Roger Espasa, Intel
Rudolf Eigenmann, Purdue U
Sandhya Dwarkadas, U of Rochester
Siegfried Benkner, U of Vienna
Timothy Jones, U of Cambridge
Walid Najjar, UCR
Yanos Sazeides, Cyprus U

ACM Student Research Competition Selection Committee:
----------
Erik Altman (Chair)

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 * Call for Papers: ICCD 2013
http://www.iccd-conf.com/
Submitted by Rainer Buchty <[log in to unmask]>

31st IEEE International Conference on Computer Design
ICCD 2013

THEME: The Next 30 Years

Asheville, NC, USA
October 6-9, 2013
http://www.iccd-conf.org

IMPORTANT DATES:

Abstract submission: May 6
Paper submission: May 13
Author notification: July 22
Final paper: August 26


The INTERNATIONAL CONFERENCE ON COMPUTER DESIGN encompasses a wide
range of topics in the research, design, and implementation of
computer systems and their components. ICCD's multi-disciplinary
emphasis provides an ideal environment for developers and researchers
to discuss practical and theoretical work covering system and computer
architecture, test, verification and security, design and technology,
and tools and methodologies.

In 2012, ICCD celebrated its 30th edition with a retrospective of
developments since 1983. This year, the conference theme is:

The Next 30 Years

We especially encourage submissions that look forward to future
systems and technologies. Manuscripts describing original work on any
topic from the scope of ICCD are welcome. Authors are asked to submit
technical papers in accordance to the author's instructions in one of
the following five conference tracks:

** COMPUTER SYSTEMS AND APPLICATIONS.
Advanced computer architecture for general and application-specific
enhancement; Software design for embedded, mobile, general-purpose,
cloud, and high-performance platforms; IP and platform-based designs;
HW/SW codesign; Modeling and performance analysis; Support for
security, languages and operating systems; Real-time systems;
Application-specific and embedded software optimization; Compiler
support for multithreaded and multi-core designs; Memory system and
network system optimization; On-chip and system-area networks; Support
for communication and synchronization.

** PROCESSOR ARCHITECTURE.
Microarchitecture design techniques for uni- and multi-core
processors: instruction-level parallelism, pipelining, caching, branch
prediction, multithreading; Techniques for low-power, secure, and
reliable processors; Embedded, network, graphic, system-on-chip,
application-specific and digital signal processor design; Hardware
support for processor virtualization; Real-life design challenges:
case studies, tradeoffs, post-mortems.

** LOGIC AND CIRCUIT DESIGN.
Circuits and design techniques for digital, memory, analog and
mixed-signal systems; Circuits and design techniques for high 
performance and low power; Circuits and design techniques for 
robustness under process variability and radiation; Design techniques
for emerging process technologies (MEMs, spintronics nano, quantum); 
Asynchronous circuits; Signal processing, graphic processor and
arithmetic circuits. 

** ELECTRONIC DESIGN AUTOMATION.
High-level, logic and physical synthesis; Physical planning, design
and early estimation for large circuits; Automatic analysis and
optimization of timing, power and noise; Tools for multiple-clock
domains, asynchronous and mixed timing methodologies; CAD support for
FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and
OPC methodologies; System-level design and synthesis; Tools and design
methods for emerging technologies (MEMs, spintronics, nano, quantum). 

** TEST, VERIFICATION, AND SECURITY.
Design error debug and diagnosis; Fault modeling; Fault simulation and
ATPG; Fault tolerance; DFT and BIST. Functional, transaction-level,   
RTL, and gate-level modeling and verification of hardware designs;    
Equivalence checking, property checking, and theorem proving;
Constrained-random test generation; High-level design and SoC
validation. Hardware security primitives; Side channel analysis; Logic
and microarchitectural countermeasures; Interaction between VLSI test 
and trust.

ICCD 2013 Organizing Committee

General Chairs
  Greg Byrd, NC State Univ., USA
  Klaus Schneider, Univ. of Kaiserslautern, Germany
Past Chair
  Sofiene Tahar, Concordia Univ., Canada
Technical Program Chairs
  Pradip Bose, IBM, USA 
  Naehyuck Chang, Seoul National Univ., Korea
Special Sessions Chair
  Omer Khan, Univ. of Connecticut, USA
Finance Chairs
  Carlo Galuzzi, TU Delft, The Netherlands
  Andrew Hilton, Duke Univ., USA
Local Arrangements Chair
  James Tuck, NC State Univ., USA
Publication Chair
  Sung Woo Chung, Korea Univ., Korea
Web Chair
  John Kim, KAIST, Korea
Publicity Chairs
  Rainer Buchty, TU Braunschweig, Germany
  Yukuen Lai, Chung Yuan Christian Univ., Taiwan
  Guru Prasadh Venkataramani, GWU, USA

ICCD 2013 Track Chairs

Computer Systems and Applications
  Luc Claesen, Hasselt Univ., Belgium
  Natalie Enright Jerger, Univ. of Toronto, Canada
Processor Architecture
  Ben Juurlink, TU Berlin, Germany
  Sung Woo Chung, Korea Univ., Korea
Logic and Circuit Design
  Massimo Alioto, Univ. of Siena, Italy
  William Hung, Synopsys, USA
Electronic Design Automation 
  David Pan, Univ. of Texas, USA
  Donatella Sciuto, Politecnico di Milano, Italy
Test, Verification, and Security
  Ozgur Sinanoglu, NYU Abu Dhabi, UAE
  Dominik Stoffel, Univ. Kaiserslautern, Germany

ICCD Steering Committee

Kee-Sup Kim, Samsung, Korea (Chair)
Peter-Michael Seidel, Univ. of Hawaii, USA
Sandip Kundu, Univ. of Massachusetts, USA 
Georgi Gaydadjiev, Chalmers Univ., Sweden

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 * Call for Papers: ICAC 2013 
https://www.usenix.org/conference/icac13
Submitted by Ming Zhao <[log in to unmask]>

10th International Conference on Autonomic Computing

June 26-28, 2013  San Jose, CA
Co-held with the 2013 USENIX Federated Conferences Week
Sponsored by USENIX, the Advanced Computing Systems Association

* Important Dates
  Paper registrations (title and abstract) due: February 25, 2013,
11:59 p.m. PST
  Paper submissions due: March 4, 2013, 11:59 p.m. PST
  Notification to authors: April 8, 2013
  Final paper files due: May 22, 2013

* Overview
  ICAC is the leading conference on autonomic computing techniques,
foundations, and applications. Large-scale systems of all types, such
as data centers, compute clouds, sensor networks, embedded or
pervasive environments, and the Internet of Things are becoming
increasingly complex and burdensome for people to manage. Autonomic
computing systems reduce this burden by managing their own behavior in
accordance with high-level goals. In autonomic systems, resources and
applications are managed to maximize performance and minimize cost,
while maintaining predictable and reliable behavior in the face of
varying workloads, failures, and malicious threats. Achieving
self-management requires and motivates research that spans a wide
variety of scientific and engineering disciplines, including
distributed systems, artificial intelligence, machine learning,
modeling, control theory, optimization, planning, decision theory,
user interface design, data management, software engineering, emergent
behavior, and bio-inspired computing. ICAC brings together researchers
and practitioners from disparate disciplines, application domains, and
perspectives, enabling them to discover and share underlying
commonalities in their approaches to making resources, applications,
and systems more autonomic.

* Topics
  Papers are solicited from all areas of autonomic computing,
including (but not limited to):
  ** Self-managing components, such as compute, storage, and
networking devices; embedded and real-time systems; and mobile devices
such as smart phones
  ** AI and mathematical techniques, such as machine learning, control
theory, operations research, probability and stochastic processes,
queuing theory, rule-based systems, and bio-inspired techniques, and
their use in autonomic computing
  ** End-to-end design and implementations for management of
resources, workloads, availability, performance, reliability,
power/cooling, security, and others
  ** Monitoring systems that can scale to large environments
  ** Hypervisors, operating systems, middleware, or application
support for autonomic computing
  ** Novel human interfaces for monitoring and controlling autonomic systems
  ** Goal specification and policies, including specification and
modeling of service-level agreements, behavior enforcement, IT
governance, and business-driven IT management
  ** Frameworks, principles, architectures, and toolkits, from
software engineering practices and experimental methodologies to
agent-based techniques
  ** Automated management techniques for emerging applications,
systems, and platforms, including social networks, Big Data systems,
multi-core processors, and Internet of Things
  ** Fundamental science and theory of self-managing systems for
understanding, controlling, or exploiting emergent system behaviors to
enforce autonomic properties
  ** Applications of autonomic computing and experiences with
prototyped or deployed systems solving real-world problems in science,
engineering, business, or society
  
  Papers will be judged on originality, significance, interest,
correctness, clarity and relevance to the broader community. Papers
are strongly encouraged to report on experiences, measurements, user
studies, and provide an appropriate quantitative evaluation if at all
possible.

* Paper Submissions
  Full papers (a maximum of 10 pages) and short papers (4 pages) are
invited on a wide variety of topics relating to autonomic computing.
Both full and short papers should be typeset in two-column format in
10 point type on 12 point (single-spaced) leading, with the text block
being no more than 6.5" wide by 9" deep. Both kinds of papers should
be submitted via the Web submission form, which will be available here
soon. Complete formatting and submission instructions can be found
here. Authors are also encouraged to submit a poster or demo that
summarizes or augments their paper (see below).

  Simultaneous submission of the same work to multiple venues,
submission of previously published work, or plagiarism constitutes
dishonesty or fraud. USENIX, like other scientific and technical
conferences and journals, prohibits these practices and may take
action against authors who have committed them. See the USENIX
Conference Submissions Policy for details. Papers accompanied by
nondisclosure agreement forms will not be considered. If you are
uncertain whether your submission meets USENIX's guidelines, please
contact the program co-chairs, [log in to unmask], or the USENIX
office, [log in to unmask]

  At least one author of an accepted paper is expected to present the
paper in person at the conference. The accepted papers will be
available online to registered attendees before the conference and
will also appear in proceedings distributed via USB drives at the
conference. If your accepted paper should not be published prior to
the event, please notify [log in to unmask] The papers will be
available online to everyone beginning on June 26, 2013. Accepted
submissions will be treated as confidential prior to publication on
the USENIX ICAC'13 Web site; rejected submissions will be permanently
treated as confidential.

* Special Tracks
  To facilitate community collaboration and exchange of ideas in emergent technological areas, ICAC'13 will host two special 
tracks, each of which will be reviewed by its own subcommittee. More information regarding the special track on Self-Aware Internet of Things and the special track on Management of Big Data 
Systems is available on the ICAC'13 Call for Papers Web site.

* Posters and Demonstrations
  ICAC'13 will also feature a poster and demonstration session consisting of research prototypes and technology artifacts that 
demonstrate autonomic software or autonomic computing principles. Formatting and submission instructions, plus the Web 
submission form specific to this session, is available on the Call for Papers Web site.

* Ph.D. Forum
  Current Ph.D. students who are working on topics relevant to autonomic computing are invited to submit a short summary 
(up to 2 pages) of their work. Top selected submissions will be presented at a Ph.D. forum during the ICAC'13 conference, 
to receive constructive feedback from experts in the field and peers. Top selected submissions will be presented at a PhD forum 
during the ICAC'13 conference. Please check the Call for Papers Web site for submission instructions.

* Workshops
  Workshops will take place in conjunction with ICAC'13 during USENIX Federated Conferences Week. Find out more at www.
usenix.org/conference/icac13/workshops.


* Conference Organizers:
  Please see the website (https://www.usenix.org/conference/icac13).

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 * Call for Participation: ISPASS 2013 Workshops and Tutorials
Submitted by Ioana Baldini <[log in to unmask]>

The following two tutorials and one workshop are being held on 
Sunday April 21, 2013 in conjunction with ISPASS:

Modeling Exascale Applications with SST/macro and Eiger 
(half day)
(http://casl.gatech.edu/research/eiger-tutorial)

GPUWattch + GPGPU-Sim: An Integrated Framework for
 Energy Optimizations in Manycore (half day) 
(http://ready.ece.utexas.edu/workshops/gpuwattch/)

FastPath 2013 Workshop on Performance Analysis
 of Workload Optimized Systems (full day)
(http://researcher.watson.ibm.com/researcher/view_project.php?id=4338)
Submission deadline: March 10, 2013

Detailed information:

Modeling Exascale Applications with SST/macro and Eiger
(half day)

In high performance computing (HPC), the importance of fast, large
scale models of high fidelity are only increasing as we move towards
the next frontier of exascale. Hardware/software codesign is viewed as
a key methodology to reaching this end. The SST/macro toolkit[1]
provides HPC engineers the ability to explore current and future
hardware/software design constraints. Instead of costly (in time and
user effort) cycle-accurate simulation, macro-scale simulation can
provide valuable insight into the performance of large
applications. The value of these tools lies in high quality
application models for increasingly complex hardware designs.

The Eiger Performance Modeling Framework[2] generates models by
applying statistical techniques from the field of machine learning on
empirical performance data. While macro-scale simulation can provide a
reasonable overview of system wide phenomena, Eiger can leverage data
acquired from micro-scale sources to inform large scale simulations in
SST/macro. Eiger provides an API and data store for aggregating data
from micro-scale sources such as simulators, emulators, and runtime
instrumentation.

This tutorial will present attendees with the techniques and
methodologies to leverage SST/macro and Eiger for modelling large
scale applications on upcoming supercomputer hardware. This
presentation is geared towards domain experts and HPC hardware
designers, as well as students and researchers whose work requires
exploration of programming models, interaction between computation and
communication, and data-driven modelling techniques for large scale
systems. These tools are geared toward ease of use and rapid
iteration, allowing area experts to generate verbose performance
models without requiring intricate knowledge of every facet of the
computing environment. This tutorial will require only a basic level
of programming skill.

GPUWattch + GPGPU-Sim: An Integrated Framework for 
Energy Optimizations in Manycore (half day) 

The objective of this tutorial is to present an overview of the design
and implementation of the GPGPU- Sim simulation infrastructure along
with a newly developed power model. The integrated GPUWattch power
model is highly configurable and extensible.

GPGPU-Sim version 3.x represents a significant update to GPGPU-Sim,
featuring a more accurate and detailed microarchitectural model. It
includes support for NVIDIA's native ISA and the Fermi
Architecture. With the tightly-coupled GPUWattch, the simulation
infrastructure is now a complete platform for performance and energy
optimization research. The infrastructure follows a rigorous design
methodology that has been tested and validated against hardware
performance and power measurements for both the Fermi and Quadro
architectures.


FastPath 2013 Workshop on Performance Analysis
 of Workload Optimized Systems (full day)

The goal of FastPath is to bring together researchers and
practitioners involved in cross-stack hardware/software performance
analysis, modeling, and evaluation of workload optimized systems.

With microprocessor clock speeds being held constant, optimizing
systems around specific workloads is an increasingly attractive means
to improve performance. The importance of workload optimized systems
is seen in their ubiquitous deployment in diverse systems from
cellphones to tablets to routers to game machines to Top500
supercomputers, and IT appliances such as IBM's DataPower and Netezza,
and Oracle's Exadata.

More precisely, workload optimized systems have hardware and/or
software specifically designed to run well for a particular
application or application class. The types and components of workload
optimized systems vary, but a partial list includes traditional CPUs
assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators,
I/O accelerators, hybrid systems, and IT appliances.

Exploiting CPU savings and speed-ups offered by workload optimized
systems for application level performance improvement poses several
cross stack hardware and software challenges. These include developing
alternate programming models to exploit massive parallelism offered by
accelerators, designing low-latency, high-throughput H/W-S/W
interfaces, and developing techniques to efficiently map processing
logic on hardware.

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 * Call for Participation: PACT 2013 ACM Student Research Competition
https://www.easychair.org/conferences/?conf=pact2013src
Submitted by Ioana Baldini <[log in to unmask]>

IMPORTANT DATES 

Abstract submission:            11:59pm Eastern Time Friday June 21, 2013
Acceptance notification:        11:59pm Eastern Time Friday July 12, 2013 

SUBMISSIONS 

Submissions to the PACT 2013 ACM Student Research Competition (SRC)
must be submitted electronically at the site below: 

https://www.easychair.org/conferences/?conf=pact2013src 

The submission should be in pdf format. Blind submissions are fine,
but not required.  Submissions should not exceed 1 page, and should
not exceeding 800 words.  Figures and References are fine, and must
fit within the single page.  You may use this latex template:
http://www.cs.utah.edu/~rajeev/pactformat.tar.gz 

This template will format the paper in the style here:
http://www.cs.utah.edu/~rajeev/pactformat.pdf 

OVERVIEW 

The 21st International Conference on Parallel Architectures and
Compilation Techniques (PACT) invites participation in the ACM Student
Research Competition (SRC). Sponsored by ACM and Microsoft Research,
the SRC is a forum for undergraduates and graduate students to share
their research results, exchange ideas, and improve their
communication skills while competing for prizes. Students accepted to
participate in the SRC are entitled to a travel grant (up to $500) to
help cover travel expenses. The top 3 undergraduate and graduate
winners will receive all of the following prizes: 

  1. Monetary prizes of $500, $300, and $200, respectively. 

  2. An award plaque and a two-year complimentary ACM membership
    with a subscription to ACM's Digital Library. 

  3. The names and research abstracts of the winners will be posted
    on the ACM SRC web site. 

  4. An invitation to participate in the SRC Grand Finals, an on-line
    round of competitions among the winners of individual
    conference-hosted SRCs. The top three graduate and undergraduate
    Grand Finalists will receive an additional $500, $300, and $200,
    respectively, along with Grand Finalist plaques. Grand Finalists and
    their advisors will be invited to the Annual ACM Awards Banquet for
    an all-expenses-paid trip, where they will be recognized for their
    accomplishments, along with other prestigious ACM award winners,
    including the winner of the Turing Award. 

The SRC consists of two rounds: a poster session and a presentation
session. A panel of judges will select a number of finalists from the
poster session, who will be invited to the presentation session at
PACT 2013 and compete for the prizes. The evaluation will be
concentrated on the quality of both visual and oral presentation, the
research methods, and the significance of contribution. 

You can find more information on the ACM Student Research Competition at 
http://src.acm.org

ELIGIBILITY 

A participant in the SRC must meet all following conditions: 

  1. The participant must submit an up to 800-word abstract
    outlining the content of a poster that is going to be presented
    during the competition. The abstract must include the poster
    title, author names, affiliations, and the name of the academic
    advisor. It should describe the research problem, motivation and
    background, techniques and results, and the prospect for clearly
    and concisely conveying the work in a poster format. It should
    state the novelty and contributions of the work explicitly. The
    submission deadline is Friday June 21, 2013, at 11:59 pm US
    Eastern Time. 

  2. The abstract can have some overlap with previous publications
    (including PACT-2013), but some significant part of it must have
    not appeared before. Novelty is one of the criteria for
    selection. 

  3  The abstract and the poster must be authored solely by the
    participant. 

  4. The participant must be an ACM student member, and must
    maintain an undergraduate or graduate student status as of June
    21, 2013. Please indicate whether you are an undergraduate or
    graduate student. 

For each accepted SRC poster, a one-page extended abstract in the ACM
format will be included in the PACT-2013 conference proceedings. The
content, however, can be included in a future submission to other
conferences or journals. 

SELECTION COMMITTEE 

Chair:  Erik Altman, IBM T.J. Watson Research Center 

Rajeev Balasubramonian,         University of Utah
Luis Ceze,                      University of Washington
Jack Davidson,                  University of Virginia
Evelyn Duesterwald,             IBM T.J. Watson Research Center
R. Govindarajan,                Indian Institute of Science
Jason Mars,                     University of California, San Diego
Andreas Moshovos,               University of Toronto
Gilles Pokam,                   Intel
Xipeng Shen,                    William and Mary
Antonia Zhai,                   University of Minnesota
Cliff Young,                    DE Shaw Research 

CONTACT
For questions regarding the submission process, or for additional
information, clarifications, or questions, please contact the ACM
Student Research Competition Chair, Erik Altman ([log in to unmask])

SPONSORS
The ACM Student Research Competition at PACT-2013 is sponsored by the
ACM and Microsoft Research.

WINNERS FROM 2012 

#1: Transactional Event Profiling in a Best-Effort Hardware
   Transactional Memory System
     o Matthew Gaudet, University of Alberta 

#2: Efficient Data Compression for Memory Hierarchies
     o Gennady Pekhimenko, Carnegie Mellon University 

#3: Transparent Runtime Deadlock Elimination
     o Hari K. Pyla, Virginia Tech

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 * Call for Participation: Using Queuing Theory to Model Data Center Systems
http://www.eecs.umich.edu/BigHouse/
Submitted by Thomas Wenisch <[log in to unmask]>

Using Queuing Theory to Model Data Center Systems
Tutorial with ASPLOS 2013
3/17 1:30-5:00pm

David Meisner, Facebook, [log in to unmask]
Mor Harchol-Balter, Carnegie Mellon University, [log in to unmask]
Thomas Wenisch, University of Michigan, [log in to unmask]

Recently, there has been an explosive growth in Internet services, greatly 
increasing the importance of data center systems. Applications served from 
ithe cloudi are driving data center growth and quickly overtaking traditional 
workstations. Although there are many analytic and simulation tools for 
evaluating components of desktop and server architectures in detail, scalable 
modeling tools are noticeably missing.

We believe that stochastic methods and queueing theory together provide an 
avenue to answer important questions about data center systems. In the first 
half of this tutorial, we present a crash-course (or perhaps, a refresher for
some) on the essential elements of queueing theory with particular applications
to modeling data center systems. We also illustrate how queueing theory can be
used to solve problems related to the design and analysis of computer systems.

In the second part of the tutorial, we describe BigHouse, a simulation 
infrastructure that combines queuing theory and stochastic methods to model 
data centers systems. Instead of simulating servers using detailed 
microarchitectural models, BigHouse raises the level of abstraction using the
tools of queuing theory, enabling simulation at 1000-server scale in less 
than an hour. We include brief background on data center power modeling, a
description of the statistical methods used by BigHouse, parallelization 
techniques, a tour of the simulator code, and a case study of using BigHouse
to model data center power capping.

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 * Call for Papers: ACM TACO 2.0
http://mc.manuscriptcentral.com/taco  
Submitted by Tom Conte <[log in to unmask]>

Over the last two years ACM TACO has optimized its internal
processes. Today, the average turnaround time from submission to first
response is 55 days which is less than two months. For revised
manuscripts, the review process goes even faster. In 2012, most
accepted manuscripts went through two rounds of reviews to reach a
final decision only 5 months after submission. Accepted manuscripts
are printed in the next ACM TACO issue -- which means an extra delay
of at most 3 months. Hence, excellent manuscripts can make it from
submission to print in 6 months; papers needing a major revision will
make it to print in at most 9 months. The ACM TACO acceptance rate
after two review rounds was 24% in 2011; it is 26% in 2012. We call
this "ACM TACO 2.0."

ACM TACO 2.0 now has a review cycle and an acceptance rate which is
competitive with the best ACM conferences, but without the
inconvenient non-negotiable submission deadlines, and with the
advantage of being able to revise a paper based on the detailed review
reports by carefully selected reviewers, and of being published as
soon as it is accepted. On top of that, authors of original work
papers get an open invitation to present their paper at the yearly
HiPEAC conference, which is the premier European network event on
topics central to ACM TACO, attended by more than 500 scientists.

For the 2013 ACM TACO 2.0 issues, we are calling for high-quality
manuscripts on topics included, but not limited to:
-Computer system architectures and processor architectures, including
 multiprocessors and multithreaded computers
-Interaction of operating systems, compilers, programming languages,
 and architecture
-Feedback-Directed Software/Hardware Optimization
-Dynamic compilation, adaptive execution, and continuous profiling/optimization.
-Virtual machine, binary translation hardware, and software optimizations
-Compiler optimizations that exploit instruction level parallelism,
 such as software pipelining, global scheduling, register allocation,
 and memory disambiguation
-Advanced software and hardware speculation, prediction, and
 predication techniques.
-High-performance microarchitecture innovation (e.g., VLIW,
 superscalar, multithreaded, etc.)
-Architectures and compilers for embedded processors, application
 specific processors and DSPs, including network and router
 architectures
-Memory system optimization
-Parallel processing
-Architecture or compiler-based power and energy optimization
-Application characterization and architectural implications
-Performance evaluation and measurement of real systems
-Papers of interest to the SIGMICRO, SIGARCH, and SIGPLAN community

There is no deadline but manuscripts are processed on a
first-come-first-served basis. Submit your best work via
http://mc.manuscriptcentral.com/taco as soon as it is ready to go. We
will work hard to get back to you in 2 months with your reviews.

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 * Call for Papers: IEEE Micro Special Issue on Dark Silicon
https://mc.manuscriptcentral.com/micro-cs
Submitted by Michael Bedford Taylor <[log in to unmask]>

Call for Papers, IEEE Micro Special Issue on Dark Silicon 
Guest Editors:  Michael Taylor and Steven Swanson (UCSD)

Submissions due:   March 8, 2013
Publication date:  Sept-Oct 2013


Over the last five years, the phenomenon known as Dark Silicon has
emerged as the most fundamental factor that shapes our ability to
exploit the exponentially increasing resources that Moore's Law
provides. Dark Silicon refers to the exponentially increasing number
of a chip's transistors that must remain passive, or "dark", in order
to stay within a chip's power budget.

Due to the breakdown of Dennard Scaling, multicore chips will not
be able to scale with die area; the fraction of a chip that can be
filled with cores running at full frequency is dropping exponentially
with each process generation. This reality will force designers to
ensure that, at any point in time, large fractions of their chips are
effectively dark or dim -- either idle or significantly underclocked.
As exponentially larger fractions of a chip's transistors become dark
transistors, silicon area becomes an exponentially cheaper resource
relative to power and energy consumption. This shift calls for new
architectural techniques that "spend" silicon area to "buy" energy
efficiency, or for new circuit technologies that overcome the inherent
limitations of CMOS that lead to dark silicon. To this end, this IEEE
Micro issue seeks original papers on all topics related to dark
silicon that span the spectrum of layers in the system stack, from
device, circuit and architecture design to the role of software in
maximize computing capabilities in the face of dark silicon.

Areas of interest include, but are not limited to:

- Approaches that offer new insight into the dark silicon problem
- Architectural approaches to managing and exploiting dark silicon
- Scalable design and synthesis techniques for customizable and
specialized cores
- Promising Beyond-CMOS approaches that enable post-Dennardian circuit scaling
- Novel applications for idle chip area
- Software systems for adapting to dark silicon
- Power management techniques for dark silicon
- Energy/power-efficient circuit designs and memory systems for dark silicon

Submission procedure:

Please log onto IEEE CS Manuscript Central
(https://mc.manuscriptcentral.com/micro-cs) to submit your manuscript
to the "Dark Silicon" issue.  Please direct questions to the IEEE
Micro magazine assistant ([log in to unmask]).  For the manuscript
submission, acceptable file formats include Microsoft Word and PDF.
Manuscripts should not exceed 5,000 words including references, with
each average-size figure counting as 150 words toward this limit.
Please include all figures and tables, as well as a cover page with
all the relevant author contact information (name, postal address,
phone, fax, and e-mail address) and a 200-word abstract. Submitted
manuscripts must not have been previously published or currently
submitted for publication elsewhere, and all manuscripts must be
cleared for publication. All previously published papers must have at
least 30% new content compared to any conference (or other)
publication. Accepted articles will be edited for structure, style,
clarity, and readability. For more information, please visit the IEEE
Micro Author Center
(http://www2.computer.org/portal/web/peerreviewmagazines/acmicro)

Important dates:
Initial submissions due: March  8, 2013
Author notification:     April 30, 2013
Final version due:       June  14, 2013
Publication timeframe:   Sept-Oct, 2013

Questions:

For any further information and questions please contact Guest Editor
Michael Taylor ([log in to unmask]).

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 * Call for Presentations: 2nd Dark Silicon Workshop (DaSi 2013)
http://darksilicon.ucsd.edu
Submitted by Jack Sampson <[log in to unmask]>

The 2nd Dark Silicon Workshop
Tel-Aviv, Israel.
June 24th, 2013. Held in conjunction with ISCA 2013

The second Dark Silicon Workshop provides a unique forum for discussing
the challenges and opportunities that Dark Silicon presents. There are
many research questions left to answer before new architectures built
specifically to mitigate or exploit dark silicon become the default
platforms for general purpose computing. To scale alongside dark
silicon, architects will need to design and verify specialized
processors in increasing numbers. Making heterogeneous platforms easy
to program will require us to reconsider traditional language and OS
abstractions. Traditionally, many of the performance gains from
specialized hardware stem from customized memory designs, and it is
not yet clear how best to integrate multiple such memory designs
together into a single architecture. These and other challenges will
face researchers as they shed light on silicon's dark future.

The organizing committee is soliciting presentations on any topic
related to Dark Silicon, including (but not limited to):
- Architectural approaches to managing and exploiting dark silicon
- Power management techniques
- Energy/power-efficient circuit designs
- Energy/power-efficient memory systems
- Scalable design and synthesis techniques for customizable and
specialized cores
- Novel applications for idle chip area

The goal is to facilitate the exchange of the latest ideas, insights,
and knowledge that can propel future progress. In lieu of printed
proceedings, we will post the slides and extended abstracts of the
presentations online. Presentation of new work at the workshop does
not preclude future publication.

Workshop submissions should be in the form of a 2-page presentation
abstract.  Submissions will be evaluated on the basis of impact,
novelty, and general interest.  The submission deadline is March 29,
2013, with notification of acceptance by May 10, 2013.

Further details on abstract submission, technical program, tutorials,
travel, social program, and travel grants will be provided at the
workshop website:

http://DarkSilicon.ucsd.edu

Organizing Committee:
Jack Sampson, UCSD
Steven Swanson, UCSD
Michael B. Taylor, UCSD

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 * Call for Papers: MCsoC-13
http://www.mcsoc-forum.org/ 
Submitted by Abderazek Ben Abdallah <[log in to unmask]>
 
IEEE 7th International Symposium on Embedded Multicore SoCs (MCsoC-13), NII, 
Tokyo, Japan, September 26-28, 2012.

Paper Submission
March 31, 2013

Notification of Acceptance
May 15, 2013

Camera ready paper
June 15, 2013

Symposium Date	September 26-28, 2013

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 * Call for Papers: ICPP-EMS'2013
https://sites.google.com/site/icppems2013/home
Submitted by Kuan-Ching Li <[log in to unmask]>

The 2013 International Workshop on Embedded Multicore Systems
To be held in conjunction with
The 42nd International Conference on Parallel Processing (ICPP'2013)

October 1-4, 2013    Lyon, France

Embedded systems with Multicore designs are of major focuses from both
industry and academia. While embedded Multicore systems will look to
play an important role ahead for system designs, many challenging
issues remain. Applications, programming models, architecture designs,
emerging memory architectures, and software tools all need to help for
the advance of embedded Multicore computing ahead.

The 2013 International Workshop on Embedded Multicore Systems
(ICPP-EMS 2013) will bring researchers and experts together to present
and discuss the latest developments and technical solutions concerning
various aspects of embedded Multicore computing.

ICPP-EMS 2013 seeks original unpublished papers focusing on emerging
applications, embedded compilers, embedded memory and architecture
design, DSP/GPU systems, ESLs, embedded Multicore programming models,
and WCET analysis. Moreover, ICPP-EMS 2013 also welcomes
work-in-progress, case studies, visionary idea, new application
challenges, and industrial practice studies.

Topics of Interest
- Memory Architectures for embedded Multicore systems
- Design for emerging embedded memory systems
- Compilers for DSP processors
- Embedded Multicore processors
- Compilers for heterogeneous embedded Multicore systems.
- Programming models for embedded Multicore systems
- Signal processing on embedded Multicore systems
- Multimedia signal processing algorithms on embedded Multicore systems
- Multimedia applications on embedded Multicore systems
- Human-computer interaction on Multicore systems
- Augmented reality applications on Multicore systems
- Software for Multicore, GPU, and embedded architectures
- VM for embedded systems
- 3D IC and Multicore architectures
- Real-time system designs for embedded Multicore environments
- Compiler for low-power
- ESL designs for embedded Multicore systems
- Applications for Automobile electronics of Multicore designs
- Embedded OS designs and performance tuning tools
- hardware/software co-design framework
- embedded devices + cloud computing framework
- Compiler for worst-case execution time analysis
- Formal method for embedded systems

Submission
Papers should present original research and should provide sufficient
background material to make them accessible to the community. Full
paper submissions should not exceed 10 pages in standard IEEE
conference format. Papers should be submitted electronically through
the workshop web site at Easychair
https://www.easychair.org/conferences/?conf=icppems2013

Important dates
Submission due date: May 1, 2013
Notification date: June 15, 2013
Camera Ready due date: July 15, 2013
EMS Workshop date: October 3, 2013
ICPP Conference dates: October 1-4, 2013

Organizers
General Chairs
Albert Cohen, INRIA, France
Jenq Kuen Lee, National Tsing-Hua University, Taiwan

Program Chairs
Barbara Chapman, University of Houston, USA
Kuan-Ching Li, Providence University, Taiwan

Contact
For additional information, please send your email to [log in to unmask]

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