This is the 1st July 2008 Digest of SIGARCH Messages (sigarch-jul08a):
* NOTE: Nate Binkert succeeds Doug Burger as SIGARCH Information Director
http://www.sigarch.org
Submitted by Nate Binkert <[log in to unmask] OR [log in to unmask]>
* Reminder to Download Architecture Papers from the ACM Digital Library
Submitted by Doug Burger <[log in to unmask]>
* HPCA 2009 Call for Papers: IEEE International Symposium on High Performance Computer Architecture
http://www.hpcaconf.org/hpca15
Submitted by James Tuck <[log in to unmask]>
* CACTI 5.2 release: Support for embedded and commodity DRAM modeling
http://www.hpl.hp.com/research/cacti/
Submitted by Norm Jouppi <[log in to unmask]>
* NVIDIA Research Summit - Call for Posters (NOTE: deadline Aug. 1)
http://www.nvision2008.com/Professionals/researchsummit-dev.cfm
Submitted by Kevin Skadron <[log in to unmask]>
* Call for Papers: Architecture and Microarchitecture Track (D10) at DATE 2009
http://www.date-conference.com
Submitted by Christos Kozyrakis <[log in to unmask]>
* QEST 2008 Call for Participation
http://www.qest.org/qest2008/
Submitted by Nihal Pekergin<[log in to unmask]>
* InfoSys 2009 Call for Papers
http://www.iaria.org/conferences2009/InfoSys09.html
Submitted by Jaime Lloret Mauri <[log in to unmask]>
* New papers published online by IEEE Computer Architecture Letters
http://www.comp-arch-letters.org
Kevin Skadron <[log in to unmask]>
-Doug Burger
SIGARCH Chair
* Archive: http://lists.cs.wisc.edu/archive/sigarch-members/
* Web pages: http://www.cs.wisc.edu/~arch/www/, http://www.acm.org/sigarch/
* To remove yourself from the SIGARCH mailing list:
mail [log in to unmask] with message body: unsubscribe SIGARCH-MEMBERS
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Doug Burger Office: 99-2446
Principal Researcher Phone: 425-538-1668
Microsoft Research E-mail: [log in to unmask]
1 Microsoft Way www.cs.utexas.edu/users/dburger
Redmond, WA 98052
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* NOTE: Nate Binkert succeeds Doug Burger as SIGARCH Information Director
Effective today, Dr. Nate Binkert of HP Labs will be the new SIGARCH
Information Director. His duties will include sending out this
monthly email digest and maintaining the SIGARCH web page at
http://www.acm.org/sigarch/. Please post messages by emailing Nate at
[log in to unmask] or [log in to unmask]
He will succeed Doug Burger of Microsoft Research who has been SIGARCH
Information Director since 2002.
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* Reminder to Download Architecture Papers from the ACM Digital Library
Submitted by Doug Burger <[log in to unmask]>
Dear SIGARCH Members: Please remember to download architecture papers,
when you need them, from the ACM Digital Library. Each download
creates revenue for SIGARCH, which can be used for reducing conference
expenses and membership fees.
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* HPCA 2009 Call for Papers: IEEE International Symposium on High
Performance Computer Architecture
The International Symposium on High-Performance Computer Architecture provides a high-quality
forum for scientists and engineers to present their latest research findings in this rapidly-
changing field. Authors are invited to submit papers on all aspects of high-performance
computer architecture. Topics of interest include, but are not limited to:
- Processor architectures
- Cache and memory architectures
- Parallel computer architectures
- Impact of technology on architecture
- Power-efficient architectures and techniques
- Reliable architectures
- Secure architectures
- High-performance I/O systems
- Embedded and reconfigurable architectures
- Special purpose processors and accelerators
- Interconnect and on-chip network architectures
- Network processor architectures
- Innovative hardware/software trade-offs
- Impact of compilers and operating systems on architecture
- Performance modeling and evaluation
Authors should submit an abstract by Sunday, August 10, 2008, 11pm EST. They should submit
the full version of the paper by Sunday, August 17, 2008, 11pm EST. No extensions will be
granted. The full version should be a PDF file formatted according to the instructions in
http://www.hpcaconf.org/hpca15. Papers that do not adhere to the formatting instructions or
that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed.
Additionally, papers should be submitted for blind review. Submission issues should be
directed to the Program Chair at [log in to unmask] We anticipate making a Best Paper award;
all papers will be considered for nomination. Papers will be evaluated based on their novelty,
fundamental insights, and potential for long-term contribution. New-idea papers are
encouraged.
HPCA will host an Industrial Paper Session presenting novel insights from industry (see Call
for Industry Papers at http://www.hpcaconf.org/hpca15 and direct submissions to
[log in to unmask] Workshop and tutorial proposals should be sent to the Workshop/
Tutorial Chair at [log in to unmask]
Important dates
- Abstract submission: August 10, 2008, 11pm EST (firm deadline)
- Paper submission: August 17, 2008, 11pm EST (firm deadline)
- Workshop and tutorial proposals due: September 14, 2008
- Notification of paper outcome: October 31, 2008
Sponsored by the IEEE Computer Society TC on Computer Architecture.
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* CACTI 5.2 release: Support for embedded and commodity DRAM modeling
CACTI 5.2, including support for modeling both embedded and commodity DRAM, has been released.
CACTI 5 includes a number of major improvements over CACTI 4. First, as fabrication
technologies enter the deep-submicron era, device and process parameter scaling has become
non-linear. To better model this, the base technology modeling in CACTI 5 has been changed
from simple linear scaling of the original CACTI 0.8 micron technology to models based on the
ITRS roadmap. Second, embedded DRAM technology has become available from some vendors, and
there is interest in 3D stacking of commodity DRAM with modern chip multiprocessors.
As another major enhancement, CACTI 5 adds modeling support of DRAM memories. Third,
to support the significant technology modeling changes above and to enable fair comparisons
of SRAM and DRAM technology, the CACTI code base has been extensively rewritten to become
more modular. At the same time, various circuit assumptions have been updated to be more
relevant to modern design practice. Finally, numerous bug fixes and small feature additions
have been made.
The latest CACTI tech report (version 5.1) is available at
http://www.hpl.hp.com/techreports/2008/HPL-2008-20.html. CACTI 5.2 source code can be
obtained from the new CACTI web page: http://www.hpl.hp.com/research/cacti/.
The web version of CACTI at http://quid.hpl.hp.com:9082/cacti/ has also been updated to use
CACTI 5.2.
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* NVIDIA Research Summit - Call for Posters (deadline Aug. 1)
The NVIDIA Research Summit invites submissions of posters for the Research Showcase. This poster session provides an excellent opportunity to share and discuss your latest research results with academic colleagues from many different fields and with NVIDIA researchers and engineers. Posters should describe novel or interesting research topics in parallel computing, visual computing, or applications of GPUs. We particularly invite posters describing novel applications of GPU computing and CUDA to diverse problems in scientific and engineering domains.
To submit a poster, simply email a 1-page abstract summarizing your poster in PDF form to [log in to unmask] Submitted posters will be evaluated by committee and accepted on a competitive basis according to novelty, technical soundness, and interest to the NVIDIA Research Summit audience.
*The deadline for poster submissions is August 1st.*
The NVIDIA Research Summit is a cross-disciplinary forum for those using GPUs in scientific research to network, showcase their work, and learn how GPU computing can drastically increase computational power and dramatically reduce time-to-discovery. It includes keynotes by a mix of leading academics and NVIDIA engineers, roundtables on various research topics, the poster session, and some events specifically for Research Summit attendees to network. The Research Summit is a part of NVISION'08, which gathers top visual computing professionals, world-class gamers, innovative artists and designers, and cutting-edge researchers to share their ideas, experiences, and passions. For more information about the NVIDIA Research Summit and the event program, please visit our website: http://www.nvision2008.com/Professionals/researchsummit-dev.cfm
The early registration discount period ends July 31.
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* Call for Papers: Architecture and Microarchitecture Track (D10) at DATE 2009
Call for Papers
Architecture and Microarchitecture Track (D10) at DATE 2009
Nice, France, April 20-24, 2009
The Design, Automation and Test in Europe conference and exhibition is
the
main European event bringing together design automation researchers,
users
and vendors, as well as specialists in the design, test, and
manufacturing
of electronic systems and circuits. You are invited to submit your
research
contributions to the Architecture and Microarchitecture Track
(D10). The
track is included in the Design Methods, Tools, Algorithms, and
Languages
portion of the conference.
TRACK OBJECTIVES:
The purpose of the Architecture and Microarchitecture Track of DATE is
to bring
together researchers from architecture, compilers and applications to
present
and discuss innovative research of common interest.
The track topics include but are not limited to:
* Architectural and microarchitectural design techniques
* Multicore and multithreaded architecture
* Superscalar and VLIW architectures
* Memory systems,
* Power and energy efficient architectures
* Branch prediction
* Multithreading techniques
* Compilation techniqes and tools
* Modeling and performance analysis
* Application-specific architectures
* Special purpose processors and accelerators
* Arithmetic architectures
IMPORTANT DATES:
Paper submission: Sunday, September 7th
Notification: Friday, November 17, 2008
Final version: Friday, December 12, 2008
INFORMATION FOR AUTHORS:
All manuscripts must be submitted electronically following the
instructions on
the conference Web page:
www.date-conference.com
The accepted file formats are PDF and Postscript. Submissions should
not
exceed 6 pages in length for oral-presentation and 4 pages in length
for
interactive-presentation papers, and should be formatted as close as
possible
to the final format: A4 or letter sheets, double column, single
spaced, Times
or equivalent font of minimum 10pt (templates are available on the
DATE Web
site for your convenience). To permit blind review, submissions
should not
include the author names.
For additional information, please contact the track chair, Dionisios
Pnevmatikatos ([log in to unmask]) or the DATE Program Chair, Bashir
M.
Al-Hashimi ([log in to unmask])
DATE 2009 D10 Track Organization
PROGRAM CHAIRS:
Dionisios Pnevmatikatos, Technical Univ. of Crete
Christos Kozyrakis, Stanford Univ.
PROGRAM COMMITTEE:
Todd Austin, Univ. of Michigan
Albert Cohen, Inria
Koen De Bosschere, Ghent University
Babak Falsafi, EPFL
Georgi Gaydadjiev, TU-Delft
Gokhan Memik, Northwestern Univ.
Andreas Moshovos, University of Toronto
Ronny Ronen, Intel
Toshinori Sato, Kyushu University
Yiannakis Sazeides, Univ. of Cyprus
Thomas Wenisch, Univ. of Michigan
Stefanos Kaxiras, Univ. of Patras
Laura Pozzi, Univ. of Lugano
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* QEST 2008 Call for Participation
CALL FOR PARTICIPATION
5th International Conference on Quantitative Evaluation of SysTems
September 14-17, 2008, Palais du Grand Large, Saint Malo, France
http://www.qest.org/qest2008/
Co-located with Formats 2008, the 5th International Conference on
Formal Modelling and Analysis of
Timed Systems
http://formats08.inria.fr/
*******************************************************************
The International Conference on Quantitative Evaluation of SysTems
(QEST) is the leading forum on evaluation and verification of computer
systems and networks, through stochastic models and measurements. QEST
combines four former events: PNPM (Workshop on Petri Nets and
Performance Models), PAPM (Workshop on Process Algebra and Performance
Modelling), PROBMIV (Workshop on Probabilistic Methods in
Verification), and TOOLS (Conference on Modelling Techniques and Tools
for Computer Performance Evaluation).
KEYNOTES
* Michael Littman, Autonomous Model Learning for Reinforcement Learning
* Albert Benveniste, Composing Web Services in an open world : QoS issues
* Peter Glynn, Linear Programming, Lyapunov Functions, and Performance Analysis
TUTORIALS + PROGRAMME
http://www.qest.org/qest2008/programme.php
******************************************************************
REGISTRATION
The registration fees include the following items:
* a copy of the proceedings of both QEST'08 and FORMATS'08,
* the three lunches (Monday, Tuesday, Wednesday),
* the "Cheese-and-wine" session on Monday,
* the visit to the Mont St Michel,
* and the gala diner on Tuesday evening.
Early registration (on or before August 17)
QEST Tutorials 100 Û
QEST/FORMATS registration 430 Û
QEST/FORMATS student registration 280 Û
Late registration (after August 17)
QEST Tutorials 135 Û
QEST/FORMATS registration 530 Û
QEST/FORMATS student registration 340 Û
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* InfoSys 2009 Call for Papers
InfoSys 2009, April 21-25, 2009 - Valencia/Spain
see: http://www.iaria.org/conferences2009/InfoSys09.html
InfoSys 2009 is a federated event focusing on advances topics concerning the
networking, services, autonomic and autonomous systems, and intensive services
and applications.
InfoSys 2009 continues the tradition of well-established conferences, ICNS and
ICAS, and adds new trends on intensive services and applications (INTENSIVE).
Submission deadline: November 1st, 2008
ICNS 2009, The Fifth International Conference on Networking and Services
http://www.iaria.org/conferences2009/ICNS09.html
ICAS 2009, The Fifth International Conference on Autonomic and Autonomous
Systems
http://www.iaria.org/conferences2009/ICAS09.html
INTENSIVE 2009, The First International Conference on Intensive Applications
and Services
http://www.iaria.org/conferences2009/INTENSIVE09.html
Submissions must be electronically done using the "Submit a Paper" button on the
entry page of each conference.
For details on the each conference's topics, see the individual Call for Papers
for each conference.
Unpublished high quality contributions in terms of Regular papers and Forum
posters are welcome. Workshop proposals and Panel proposals on challenging
topics are encouraged.
Extended versions of selected papers will be published in IARIA on-line Journals
(http://www.iariajournals.org) and in Special issues of different journals
mentioned on the entry page of each conference.
Submissions will be peer-reviewed, published by IEEE Computer Society Press,
posted in IEEE Digital Library, and indexed via all the IEEE indexing
agreements.
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* New papers published online by IEEE Computer Architecture Letters
Computer Architecture Letters announces our most recent papers, available now via the
IEEE Computer Society Digital Library and IEEE Xplore. We continue to seek new submissions
and remain committed to fast and accurate review. Our mean time to decision since
moving to Manuscript Central has been 26 days, with 100% of submissions
decided within two months and an acceptance rate of approximately 25%.
For more information on submission, please see
http://www.comp-arch-letters.org
To subscribe to an RSS feed of CSDL RapidPosts, go to
http://feeds.pheedo.com/ieee_computer_architecture_letters
- R. Sunkam Ramanujam and B. Lin. "Randomized Partially-Minimal Routing on Three-Dimensional
Mesh Networks." Computer Architecture Letters, vol. 7, June 2008.
[In Xplore: http://ieeexplore.ieee.org/xpls/pre_abs_all.jsp?isnumber=4357966&arnumber=4537167]
- J. Lee and X. Xiao. "A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time
Complexity." Computer Architecture Letters, vol. 7, June 2008.
[In Xplore: http://ieeexplore.ieee.org/xpls/pre_abs_all.jsp?isnumber=4357966&arnumber=4537165]
- D. Black-Shaffer and J. Balfour and W. Dally and V. Parikh and J. Park. "Hierarchical
Instruction Register Organization." Computer Architecture Letters, vol. 7, June 2008.
[In Xplore: http://ieeexplore.ieee.org/xpls/pre_abs_all.jsp?isnumber=4357966&arnumber=4537168]
- D. Pao and W. Lin and B. Liu. "Pipelined Architecture for Multi-String Matching."
Computer Architecture Letters, vol. 7, June 2008.
[In Xplore: http://ieeexplore.ieee.org/xpls/pre_abs_all.jsp?isnumber=4357966&arnumber=4537166]
- Z. Li, C. Zhu, L. Shang, R. Dick, and Y. Sun. "Transaction-Aware Network-on-Chip Resource
Reservation." Computer Architecture Letters, vol. 7, June 2008.
[In Xplore: http://ieeexplore.ieee.org/xpls/pre_abs_all.jsp?isnumber=4357966&arnumber=4545404]
- C. Gomez Requena, F. Gilabert Villamon, M. Gomez, P. Lopez, and J. Duato. "Beyond
Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network."
Computer Architecture Letters, vol. 7, June 2008.
[In Xplore: http://ieeexplore.ieee.org/xpls/pre_abs_all.jsp?isnumber=4357966&arnumber=4544509]
Abstracts
---
- R. Sunkam Ramanujam and B. Lin. "Randomized Partially-Minimal Routing on Three-Dimensional
Mesh Networks." Computer Architecture Letters, vol. 7, June 2008.
Abstract:
This letter presents a new oblivious routing algorithm for 3D mesh networks called Randomized
Partially- Minimal (RPM) routing that provably achieves optimal worstcase throughput for 3D
meshes when the network radix k is even and within a factor of 1/k2 of optimal when k is odd.
Although this optimality result has been achieved with the minimal routing algorithm O1TURN
[9] for the 2D case, the worst-case throughput of O1TURN degrades tremendously in higher
dimensions. Other existing routing algorithms suffer from either poor worst-case throughput
(DOR [10], ROMM [8]) or poor latency (VAL [14]). RPM on the other hand achieves near optimal
worst-case and good average-case throughput as well as good latency performance.
- J. Lee and X. Xiao. "A Parallel Deadlock Detection Algorithm with O(1) Overall Run-time
Complexity." Computer Architecture Letters, vol. 7, June 2008.
Abstract:
This article proposes a novel parallel, hardware-oriented deadlock detection algorithm for
multiprocessor system-on-chips. The proposed algorithm takes full advantage of hardware
parallelism in computation and maintains information needed by deadlock detection through
classifying all resource allocation events and performing class specific operations, which
together make the overall run-time complexity of the new method O(1). We implement the
proposed algorithm in Verilog HDL and demonstrate in the simulation that each algorithm
invocation takes at most four clock cycles in hardware.
- D. Black-Shaffer and J. Balfour and W. Dally and V. Parikh and J. Park. "Hierarchical
Instruction Register Organization." Computer Architecture Letters, vol. 7, June 2008.
Abstract:
This paper analyzes a range of architectures for efficient delivery of VLIW instructions for
embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and
examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3)
adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory.
The result is a hierarchical instruction register organization that provides a 56% energy
and 40% area savings over an already efficient Filter Cache.
- D. Pao and W. Lin and B. Liu. "Pipelined Architecture for Multi-String Matching."
Computer Architecture Letters, vol. 7, June 2008.
Abstract:
We present a pipelined approach to hardware implementation of the Aho-Corasick (AC) algorithm
for string matching called P-AC. By incorporating pipelined processing, the state graph is
reduced to a character trie that only contains forward edges. Edge reduction in P-AC is very
impressive and is guaranteed algorithmically. For a signature set with 4434 strings extracted
from the Snort rule set, the memory cost of P-AC is only 21.5 bits/char. The simplicity of
the pipeline control plus the availability of 2-port memories allow us to implement two
pipelines sharing the set of lookup tables on the same device. By doing so, the system
throughput can be doubled with little overhead. The throughput of our method is up to 8.8
Gbps when the system is implemented using 550MHz FPGA.
- Z. Li, C. Zhu, L. Shang, R. Dick, and Y. Sun. "Transaction-Aware Network-on-Chip Resource
Reservation." Computer Architecture Letters, vol. 7, June 2008.
Abstract:
Performance and scalability are critically-important for on-chip interconnect in many-core
chip-multiprocessor systems. Packet-switched interconnect fabric, widely viewed as the de
facto on-chip data communication backplane in the many-core era, offers high throughput and
excellent scalability. However, these benefits come at the price of router latency due to
run-time multi-hop data buffering and resource arbitration. The network accounts for a
majority of on-chip data transaction latency. In this work, we propose dynamic in-network
resource reservation techniques to optimize run-time on-chip data transactions. This idea is
motivated by the need to preserve existing abstraction and general-purpose network
performance while optimizing for frequently-occurring network events such as data
transactions. Experimental studies using multithreaded benchmarks demonstrate that the
proposed techniques can reduce on-chip data access latency by 28.4% on average in a 16-node
system and 29.2% on average in a 36-node system.
- C. Gomez Requena, F. Gilabert Villamon, M. Gomez, P. Lopez, and J. Duato.
"Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network."
Computer Architecture Letters, vol. 7, June 2008.
Abstract:
The fat-tree is one of the most widely-used topologies by interconnection network
manufacturers. Recently, it has been demonstrated that a deterministic routing algorithm
that optimally balances the network traffic can not only achieve almost the same performance
than an adaptive routing algorithm but also outperforms it. On the other hand, fat-trees
require a high number of switches with a non-negligible wiring complexity. In this paper,
we propose replacing the fat--tree by a unidirectional multistage interconnection network
(UMIN) that uses a traffic balancing deterministic routing algorithm. As a consequence,
switch hardware is almost reduced to the half, decreasing, in this way, the power
consumption, the arbitration complexity, the switch size itself, and the network cost.
Preliminary evaluation results show that the UMIN with the load balancing scheme obtains
lower latency than fat--tree for low and medium traffic loads. Furthermore, in networks
with a high number of stages or with high radix switches, it obtains the same, or even
higher, throughput than fat-tree.
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