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Sender: "Team Ada: Ada Programming Language Advocacy (83 & 95)" <[log in to unmask]>
X-To: "Karl A. Nyberg" <[log in to unmask]>
Date: Tue, 14 Nov 2006 10:47:07 -0800
Reply-To: Tom Moran <[log in to unmask]>
From: Tom Moran <[log in to unmask]>
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You didn't say the schedule.  I'm quite curious to see how the N-task 
quicksort runs on more than 2 CPU cores.

Karl A. Nyberg wrote:

>I hope soon to be the recipient of an evaluation Sun Niagara T1000 via their
>"Try and Buy" program ( and would
>like to try to make it available for folks with an application that they
>would like to run in this kind of an environment.  It will be an 8-core
>machine (which, with their "4 threads per core pipelining", well, you get
>the idea...).  If you are interested, please drop me a line.
>Applications with low floating point requirements only need apply...  Only
>one FPU on the chip...
>-- Karl --