============================================================== Call for participation to the NetFPGA Training School - NewNet@Paris to be held Jul 3rd-5th, 2017 at Telecom ParisTech, Paris, France ============================================================== Organizer: * Salvatore Pontarelli ([log in to unmask]) Logistics: * Jul 3rd-5th, 2017 * Telecom ParisTech, 46 rue Barrault 75013, Paris (Rooms H1-H2) * Local organizer: Dario Rossi ([log in to unmask]) Teachers: * Gianni Antichi, Senior Research Associate at the Computer Laboratory of the University of Cambridge * Salvatore Pontarelli, Research Associate at CNIT (Consorzio Nazionale Interuniversitario per le Telecomunicazioni) and visiting researcher at [log in to unmask] Registration: * The school is free of charge, but is necessary to register by June 14th at https://newnet.telecom-paristech.fr/index.php/events/netfpga-training-school/ * The school will accept a restricted number of students. Await for official confirmation of the acceptance of your candidature before planning the trip. Scope: The NetFPGA is an open source hardware and software platform designed for research and teaching. The need for high-speed and software programmable networks requires suitable hardware platforms for developing and testing novel network solutions. The increasing interest for the design of high-speed programmable dataplanes (such as the barefoot switches) also push toward the adoption of hardware prototype platforms where implement and verify dataplane architectures. Furthermore, the use of hybrid solutions in which FPGA and commodity servers represent another interesting research topic. In all these research fields, the NetFPGA platform is an ideal candidate prototype and develop efficient solutions. However, using NetFPGA can be difficult for network engineers that usually are not familiar with many of the hardware design concepts behind the development of FPGA systems. In this training school, we show the main characteristics of the NetFPGA and some useful applications developed on top of it. Moreover, we will present the main concepts of FPGA based designs and we will carry on a series of hand-on exercises where the students will design, verify and implement on a NetFPGA several hardware designs. The school is organized in such as way that the first day is introductory and of appeal to a broader audience, whereas the second and third days are more focused and practical. In particular, the first day introduces FPGA, NetFPGA, their toolchain and useful network applications such as the NetFPGA-based Open Source Network Tester (OSNT). The second and third days covers Verilog HDL and digital design of network applications, interleaving theoretical and practical courses to empower students with the ability to carry on their own NetFPGA based design, simulation, deployment and test. Syllabus: Day 1. (3-July-2017) * Introduction FPGA, HDL, state of the art * NetFPGA Infrastructure Life of a packet through the NetFPGA Data plane Control plane (registers/PCI interface) Module Template User Data Path * FPGA Toolchain Xilinx Vivado Design suite Simulating NetFPGA on Vivado Implementing/download NetFPGA firmware using Vivado * Open Source Network Tester (OSNT) Architecture Features Future work * Verilog HDL #1 Combinatorial blocks Sequential blocks Module instantiation * Hands-on Lab. #1 Getting started with NetFPGA: Programming the board, Sending/receiving packets, Reading stats, Configure interfaces Day 2. (4-July-2017) * Verilog HDL #2 Operators, data types Arithmetic operations Registers, memories * Hands-on Lab. #2 Design of a block computing IP CHKSUM NetFPGA Simulation * Verilog HDL #3 Initial statement, always statement Blocking/non-blocking assignment Loops * Hands-on Lab. #3 Design and simulation of a finite state machine (port knocking) in Verilog NetFPGA Simulation Day 3. (5-July-2017) * Hands-on Lab. #4 Design of a block providing programmable load balancer Software/Hardware integration NetFPGA Simulation Build Hardware * Hands-on Lab. #5 Hardware Test Hardware Debug via pre-compiled registers Hardware Debug via Integrated Logic Analyze Acknowledgments: * The NetFPGA Training school will be hosted at Telecom ParisTech and is sponsored by NewNet@Paris, Cisco’s Chair Networks for the Future'' at Telecom ParisTech. Any opinion, findings or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of partners of the Chair. -- Oo Professor > Telecom ParisTech ~ Ecole Polytechnique mail: [log in to unmask] phone: +33.1.4581.7563 fax: +33.1.4581.7158 web: http://www.enst.fr/~drossi