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"F. Britt Snodgrass" wrote:
>
> There have been several articles this year in Electronic Engineering
> Times dealing with the emerging trend of using conventional software
> languages for "System on Chip" (SoC) design.


For more info see:
http://www.systemc.org
http://www.cynapps.com

My personal opinion is that C/C++ (and Ada) are missing vital
pieces to be successfully used as a HDL (hardware description
language).

Still, if you are going to take this route (using a non HDL
to design hardware) the fine control over representation
found in Ada would be a huge advantage.



> One of the main arguments given is the
> availability of large numbers of C and Java developers
> who could quickly become SoC ASIC designers.

This argument ignores the fact that there
is much less work in learning VHDL or Verilog than
in learning hardware design.
I believe the attraction is that C and Java are essentially free
while VHDL are Verilog simulation licenses are, in comparison,
hugely expensive.

> Ada is never mentioned in these articles even
> though VHDL has some similarity to Ada.

I was originally attracted to Ada because I had learnt
VHDL and realized how good that language is.
BTW the VHDL v's Verilog debate is not unlike the
Ada V's C debate.

Cheers
Geoff